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State information managing method and communication system

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State machine bit group selection apparatus for debugging a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State machine simulator for testing computer systems

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State metric memory of viterbi decoder and its decoding method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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State recovery and failover of intelligent network adapters

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State relaxation based subsequence removal method for fast stati

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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State testing device and methods thereof

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State transfer with throw-away thread

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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State transition protocol for high availability units

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Stateful failover protection among routers that provide load...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Stateless redundancy in a network device

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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States encoding in multi-bit flash cells for optimizing...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Static random access memory (SRAM) unit and method for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Static semiconductor memory device having test mode

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Static test sequence compaction using two-phase restoration and

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Static timing analysis approach for multi-clock domain designs

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Static viterbi detector for channels utilizing a code having...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Statistical analysis of sampled profile data in the...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Statistical counters in high speed network integrated circuits

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Statistical debugging using paths and adaptive profiling

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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