Statistical counters in high speed network integrated circuits

Details Statistical counters in high speed network integrated circuits Statistical counters in high speed network integrated circuits

2000-09-26

2004-08-31

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C709S224000

Reexamination Certificate

active

06785851

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is related to computers and computer networking, and in particular, to network statistical counters.
2. Background Information
Computer networks typically keep track of events associated with data traffic. Such events can include the number of good and bad packets transmitted, the number of good and bad packets received, the number of errors in network communications, etc. Statistical counters, which are typically located on-chip (or on a single integrated circuit), count the networking events and can be probed for information by network statistical management systems to determine whether the system should change to a backup connection because of too many errors, for example.
Statistical counters, as do all components, take up space on an integrated circuit. The more counters used, the greater the area consumed. In a design that has many counters, the counters may consume a substantial portion of the total area of the integrated circuit, which can be problematic because it increases the cost of the product, which is proportional to the total area.
Because of the increase in the demand for network manageability, the number of statistical counters that are needed is constantly increasing. As the number of statistical counters increases, the amount of integrated circuit area (or silicon) consumed increases. This causes an increase in the cost of the statistical counters as part of the total cost, and further encourages attempts to reduce the area the counters consume.
Another issue arising from advances in technology is that networking events are happening much faster than with older technologies, especially in high-speed networks. One solution is to buffer events as they enter the statistical counters. This solution, however, has proven inadequate in many instances because an extra level of complexity is added to the statistical counters to control the buffers. Another solution is to increment the statistical counters faster, which requires a faster clock. A faster clock, however, translates to more power consumption and more integrated circuit area used.
In many networking environments, the operating system normally manages events. In high-speed networks, however, the operating system may be too slow to manage networking events properly. Newer networks allow the hardware statistical counters keep track of events and permit the operating system to read the counters asynchronously. This means that the operating system does not wait for the statistical counters to stop incrementing events to read the counters.
In most communication systems, hardware memory elements, which store the value of counted events, are accessed for read by two different and asynchronous elements in the system. The first element to access hardware memory elements is the element that executes the increment calculation when a counted event occurs. The second element to access hardware memory elements is the higher-level management system (e.g., a software “driver”), which reads the value of the counter for statistical management usage. Thus, one access to the hardware memory elements is to increment the value(s) stored in the hardware memory elements and another access to read the hardware memory elements. A difficulty in such systems is how to have different statistical counter values available for read by two asynchronous elements.
One solution is to have two individual lines connected to each memory element. One set of lines is multiplexed for reading by the management element and the other set of lines is connected to the elements that execute the increment action. The lines are physical lines, however, which have to be routed on the integrated circuit. This translates to more integrated circuit area consumed.


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