Reduced complexity turbo decoding scheme

Reduced complexity turbo decoding scheme

Reduced latency interleaver utilizing shortened first codeword

Reduced pattern memory in digital test equipment

Reduced pin count isochronous data bus

Reduced pin count scan chain implementation

Reduced power testing with equally divided scan paths

Reduced signal test for dynamic random access memory

Reduced signaling interface method and apparatus

Reduced signaling interface method and apparatus

Reduced state trellis decoder using programmable trellis...

Reduced table size forward error correcting encoder

Reduced-complexity max-log-APP decoders and related turbo...

Reduced-complexity sequence detection

Reduced-latency soft-in/soft-out module

Reduced-pin integrated circuit I/O test

Reduced-pin-count-testing architectures for applying test...

Reduced-state device and method for decoding data

Reducing application downtime in a cluster using...

Reducing application downtime in a cluster using...