Reduced pin count isochronous data bus

Details Reduced pin count isochronous data bus Reduced pin count isochronous data bus

1998-06-17

2000-10-17

Sheikh, Ayaz R.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Error detection for synchronization control

714799, G06F 1100

Patent

active

061346985

ABSTRACT:
An isochronous bus may includes a data signal, a data valid signal, a frame synch signal and a clock signal. The bandwidth of the data signal is partitioned into a plurality of frames. The frame rate may be selected based upon the sample rate of one of the isochronous devices connected to the isochronous bus or maybe some divisor of the data rate of the isochronous bus. Each frame is partitioned into a plurality of data channels. Each data channel transmits data from an isochronous device. A number of bit time slots are allocated to each data channel. The number of bit time slots allocated to each data channel varies based upon the sample rate of the device corresponding to the data channel. In one embodiment, each data channel is allocated more bit time slots than the nominal samples of its corresponding device. In this manner, any drift of the sample clock may be accommodated. A data valid signal is transmitted synchronous to the data signal and the clock signal. The data valid signal indicates which bit time slots include valid data. As discussed above, a data channel may be allocated more bit time slots than the expected number of samples during a frame. The drift of the sample clock of a device relative to the isochronous bus clock may be detected by monitoring the period of the data valid signal.

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