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Method and apparatus for internally trimming output drivers...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for isolating bus failure

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for isolating faulty semiconductor...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for isolating uncorrectable errors...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for just in time RAID spare drive pool...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for kernel module testing

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for L2TP forward error correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method and apparatus for limited access circuit test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for limiting power dissipation in test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for limiting soft error recovery in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method and apparatus for locating a faulty device in a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for locating critical speed paths in integr

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for lockstep processing on a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method and apparatus for logic testing an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Method and apparatus for logically rejecting previously...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Method and apparatus for loopback self testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Method and apparatus for looping back a current state to...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for low density parity check encoding...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Method and apparatus for low overhead circuit scan

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method and apparatus for low-pin-count scan compression

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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