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Low hardware overhead scan based 3-weight weighted random...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low latency data encoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low latency programmable encoder with outer systematic code...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Low noise coding for digital data interface

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Low overhead coding techniques

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low overhead input and output boundary scan cells

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low pin count, high-speed boundary scan testing

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power content-addressable-memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Low power cost-effective ECC memory system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low power cost-effective ECC memory system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low power decompression of test cubes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power mode fault recovery method, system and apparatus

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Low power operation of an address interleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low power operation of an address interleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low power path memory for viterbi decoders

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Low power scan process with connected stimulus and scan paths

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power testing of very large circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power testing of very large circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power testing of very large circuits

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Low power, high reliability specific compound functional units

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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