Low overhead input and output boundary scan cells

Details Low overhead input and output boundary scan cells Low overhead input and output boundary scan cells

2000-10-11

2004-02-17

Moise, Emmanuel L. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000, C714S733000, C714S030000, C324S765010

Reexamination Certificate

active

06694465

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The subject matter of the present application is related to subject matter disclosed in the following co-assigned, U.S. patent documents which are incorporated herein by reference:
U.S. application Ser. No. 08/358,128, filed Dec. 16, 1994, now abandoned; U.S. Pat. Nos. 5,732,091 and 5,715,254.
TECHNICAL FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs) and, more particularly, to boundary scan cells implemented at input and output pins of ICs to simplify testing of the ICs and their wiring interconnections.
BACKGROUND OF THE INVENTION
Boundary scan testing is very well known in the art and is supported by an IEEE standard (IEEE 1149.1) which details its implementation and operation modes.
FIG. 1
illustrates the logic arrangement of a prior art boundary scan cell for use in boundary scan testing at IC outputs. The boundary scan cell contains an input multiplexer (Mux
1
), a capture/shift memory (Mem
1
) such as a flip-flop or other latch circuit, an output memory (Mem
2
) such as a flip-flop or other latch circuit, and an output multiplexer (Mux
2
). Mux
1
is controlled by a select signal (Select
1
) to allow Mem
1
to load data from either the serial data input or the system data output by the IC core logic. Mem
1
loads data in response to a control signal (Control
1
). The output of Mem
1
is input to Mem
2
and is output as serial data. Mem
2
loads data from Mem
1
in response to a control signal (Control
2
). Mux
2
is controlled by a select input (Select
2
) to allow it to output to the IC's output buffer either the output of Mem
2
or the system data from the IC core logic. A plurality of these boundary scan cells can be connected serially, via the serial input and output lines, to form a boundary scan register.
In
FIG. 1
, the output boundary scan cell logic is enclosed in dotted lines. The boundary scan cell connects an output from the IC's core logic to the IC's output buffer. The output buffer outputs a high (V+) or low (G) voltage in response to the logic level it receives from Mux
2
. The boundary scan cell is realized in the same region of the IC as the core logic, i.e., the core region. In most instances, i.e. when implemented in accordance with the rules stated in the IEEE 1149.1 standard, the boundary scan cell logic is dedicated for test purposes and is not shared with system logic functions. In this way, the boundary scan cell can be accessed for non-intrusive test operations without disturbing the IC's normal functional operation.
The IEEE 1149.1 standard defines three types of test operations for boundary scan cells, a sample test operation (Sample), an external test (Extest) and internal test (Intest). Sample is a required test mode for 1149.1. During Sample, the IC is in normal operation (i.e. IC's core logic is connected to the output buffers via Mux
2
) and Mux
1
and Mem
1
are operated to capture and shift out normal IC output data. Extest is another required test mode for 1149.1. During Extest, output boundary scan cells are used to drive test data from IC outputs onto wiring interconnects, and input boundary scan cells are used to capture the driven test data at IC inputs. In this way, Extest can be used to test wiring interconnects between IC inputs and outputs on a board. Intest is an optional test mode for 1149.1. During Intest, input boundary scan cells are used to drive test data to the IC's core logic, and output boundary scan cells are used to capture the response from the core logic. In this way, Intest can be used to test IC core logic.
During normal IC operation, the output of the IC's core logic passes through Mux
2
, to the output buffer, and is driven off the IC by the output buffer. Therefore, during normal mode, the IC output function is not effected by the boundary scan cell, except for the delay introduced by Mux
2
. If, during normal operation, a Sample is performed, the boundary scan cell receives Select
1
and Control
1
input to capture system data and shift it out for inspection via the serial output.
During test operation, the output of the ICs core logic is received by the boundary scan cell for capturing and shifting, but Mux
2
is controlled by Select
2
to output the test data stored in Mem
2
to the output buffer. Therefore, during test mode, the IC core logic output function is disabled by the boundary scan cell. If, during test operation, an Extest or Intest is performed, the boundary scan cell receives Select
1
and Control
1
inputs to capture system data into Mem
1
and shift it out for inspection via the serial output. While Mem
1
is capturing and shifting data, Mem
2
outputs stable test data to the output in. After Mem
1
has completed its capture and shift operation in Extest it contains new test data to be loaded into Mem
2
. Mem
2
loads the new test data from Mem
1
in response to a signal on Control
2
. After Mem
2
receives the new test data, it is output from the IC via Mux
2
and the output buffer. The purpose for Mem
2
is to latch the IC's output at a desired test logic state while Mem
1
is capturing and shifting data. Without Mem
2
, i.e. if the output of Mem
1
were connected to Mux
2
directly, the IC's output would transition between logic (i.e. ripple) states as data is captured into and shifted through Mem
1
.
Examples of the boundary scan cell of
FIG. 1
performing Sample, Extest and Intest operations are illustrated in the timing diagram of FIG.
1
A. In the timing diagram of FIG.
1
A and all following timing diagrams, “C” indications on the Control
1
and Control
2
signals indicate a low-high-low signal sequence which, in the example circuits shown, provides the control to store data into Mem
1
and Mem
2
, respectively. Logic zero and one levels on the Select
1
and Select
2
signals indicate logic levels used to control the operation of Mux
1
and Mux
2
, respectively. Also, seven Control
1
“C” signals are used in all example timing diagrams. The first Control
1
“C” signal indicates the capture of data into Mem
1
, and the following six Control “C” signals represent the shifting of data through six serially connected boundary scan cell circuits.
In
FIG. 2
, a known improvement to the boundary scan cell of
FIG. 1
is shown. The improvement is brought about by realizing Mux
2
in the buffer region of the IC's output buffer. Relocating test logic in the IC buffer region frees up area in the IC's core logic for system (non-test) logic functions. The logic required in the IC's core region is reduced by the size of Mux
2
for each required output boundary scan cell. This leaves only the boundary scan cell's Mux
1
, Mem
1
, and Mem
2
as test logic overhead in the IC's core region. The amount of boundary scan cell logic that needs to be placed and routed in the IC's core region is reduced. The boundary scan cell of
FIG. 2
operates exactly like the one of FIG.
1
.
FIG. 3
illustrates another known improvement to the boundary scan cell of FIG.
1
. This improvement was described in 1990 by D. Bhavsar on pages 183-189 of IEEE Society Press Publication “Cell Designs that Help Test Interconnection Shorts”. The improvement allows the logic output from the output buffer to be captured and shifted out of Mem
1
during Extest. This feature allows detecting shorts between pins or to supply voltages or ground that conflict with the logic level attempting to be driven out of the output buffer. For example, during Extest, if a logic one is driven from Mem
2
the output buffer will attempt to drive out a logic one. However, if the output of the output buffer is shorted to ground a high current (or low impedance) path exists in the output buffer from V+ through the top transistor to ground, which can result in a damaged or destroyed output buffer. Similarly if Mem
2
is driving out a logic zero and the output of the output buffer is shorted to a supply voltage, a high current (low impedance) path exists through the bottom transistor to

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