Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2008-07-08
2008-07-08
Louis-Jacques, Jacques (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S701000
Reexamination Certificate
active
07398446
ABSTRACT:
A first interleaved address generator is configured to generate a first interleaved address, and a second interleaved address generator is configured to generate a second interleaved address substantially concurrently with the first interleaved address generator generating the first interleaved address. A controller is configured to disable the second interleaved address generator from generating the second interleaved address if the second interleaved address is not needed to produce a continuous stream of interleaved addresses.
REFERENCES:
patent: 4045781 (1977-08-01), Levy et al.
patent: 5392328 (1995-02-01), Schmidt et al.
patent: 5535333 (1996-07-01), Allen et al.
patent: 5737337 (1998-04-01), Voith et al.
patent: 5966729 (1999-10-01), Phelps
patent: 6272652 (2001-08-01), Starr
patent: 6549998 (2003-04-01), Pekarich et al.
patent: 6748560 (2004-06-01), Hatakeyama
patent: 6910110 (2005-06-01), Kim et al.
patent: 2003/0081576 (2003-05-01), Kim et al.
Sivakumar, R. et al, “VLSI Architectures for Computing X mod M,”IEEE Proceedings on Circuits, Devices and Systems, vol. 142, No. 5, Oct. 1995, pp. 313-320.
Heergard, C. et al. “Turbo Coding.” Kluwer Academiic Publishers, 1999, pp. 35-63.
Berrou, Claude et al. “Near Optimum Error Correcting Coding and Decoding: Turbo-Codes.”IEEE Transactions on Communications, vol. 40, No. 10, Oct. 1996, pp. 1261-1271.
Wu, Z. “Coding and Interative Detection for Magnetic Recording Channels.” Kluwer Academic Publishers, 1999, pp. 44-45.
Erfanian, Javan et al. “Reduced Complexity Symbol Detectors with Parallel Structures for ISI Channels.”IEEE Transaction on Communications. vol. 42, Feb./Mar./Apr. 1994, pp. 1661-1671.
Summers, Todd et al. “SNR Mismatch and Online Estmation in Turbo Decoding.”IEEE Transaction on Communications. vol. 41, 1998, pp. 421-423.
Pietrobon, Steven S. “Implementation and Performance Of A Turbo/Map Decoder.”International Journal of Satellite Communications, 16, 1998, pp. 23-46.
Robertson, Patrick et al. “Optimal and Sub-Optimal Maximum a Posteriori Algorithms Suitable for Turbo Decoding.” International Conference on Communications, 1995, pp. 1009-1013.
Bahl, L.R. et al. “Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate.”IEEE Trans. Inform. Theory, vol. IT-20, Mar. 1974, pp. 284-287.
Robertson, Patrick et al. “A Comparison of Optimal and Sub-Optimal MAP Decoding Algorithms Operating in the Log Domain.” IEEE 1995, pp. 1009-1013.
Worm, Alexander. “Turbo-Decoding Without SNR Estimation.” IEEE Communications Letter, vol. 4, No. 6, Jun. 2000, pp. 193-195.
Garrett David C.
Nicol Chris J.
Alphonse Fritz
Louis-Jacques Jacques
Lucent Technologies - Inc.
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