Low power path memory for viterbi decoders

Details Low power path memory for viterbi decoders Low power path memory for viterbi decoders

2000-09-01

2003-09-02

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

06615388

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to Viterbi decoders, and more specifically to a path memory for Viterbi decoders.
2. Description of the Related Art
A Viterbi decoder for decoding a transmitted convolutional code includes a branch metric calculator, ACS (add/compare/select) circuitry and a path memory. In the branch metric calculator, Hamming distances between received code words and estimated code words are calculated to produce branch metrics, which are used in the ACS circuitry to produce a number of path select command signals. The path memory is a matrix array of memory cells arranged in rows corresponding to the path select command signals. Usually, N×2
k−1
memory cells (where N is the number of stages or columns and k is the constraint length of the convolutional code) are required to implement the path memory. Since all memory cells are simultaneously operated at clock intervals and since the clock rate must be high for selecting a symbol according to the maximum likelihood sequence estimation algorithm, a significant amount of power is consumed.
Japanese Laid-Open Patent Application 8-237145 discloses a Viterbi decoder in which each memory cell of the path memory consists of two input selectors and two pairs of flip-flops. The input selectors are provided for selectively coupling the states of the N-th stage to the flip-flop pairs. The flip-flops of each pair are alternately clocked at one half the system clock rate to produce outputs for the (N+1)th stage. The outputs of the flip-flops of each pair are connected to one of intermediate selectors, which are in turn connected to two output selectors which are provided for selecting the outputs of the intermediate selectors. All selectors are controlled by signals from the ACS circuitry.
While the path memory of the aforesaid patent application becomes less complex, it requires a significant amount of modifications in the prior art ACS circuitry.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a low power path memory for a Viterbi decoder without requiring modification of ACS circuitry.
According to a broader aspect of the present invention, there is provided a path memory for a Viterbi decoder, which comprises path selecting circuitry for producing a plurality of control signals from path select command signals generated by the Viterbi decoder a T interval earlier than reference clock timing and from two path select command signals which are generated by the Viterbi decoder a 2T interval earlier than the reference clock timing corresponding to two possible states separated from each other by a predetermined distance. A matrix array of memory cells are arranged in a plurality of rows. To achieve low power consumption, these memory cells are divided into a first array of odd-numbered columns (stages) and a second array of even-numbered columns. Each row of the first-array memory cells is responsive to a corresponding one of the control signals for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing, each row of the second-array memory cells being responsive to a corresponding one of the control signals for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing, the first and second arrays alternately operating at 2T-intervals.
According to a second aspect, the present invention provides a path memory for a Viterbi decoder which generates 2
k−1
path select command signals at T-intervals, where k is the constraint length of a convolutional code. The path memory comprises path selecting circuitry for storing the 2
k−1
path select command signals generated a T interval earlier than reference clock timing. The path selecting circuitry is responsive to a path select command signal generated at the reference clock timing corresponding to each of a plurality of 2
k−1
rows for selecting, for each row, one of the stored path select command signals corresponding to two possible states which occur a 2T interval earlier than the reference clock timing and are separated from each other by a distance of 2
k−2
rows. A matrix array of memory cells is arranged in 2
k−1
rows and is divided into a first array of odd-numbered columns and a second array of even-numbered columns. Each row of the first-array memory cells is responsive to the row-corresponding path select signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing. Each row of the second-array memory cells is responsive to the row-corresponding the second-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing. The first and second arrays are alternately operating at 2T-intervals.


REFERENCES:
patent: 5923713 (1999-07-01), Hatakeyama
patent: 6374387 (2002-04-01), Van den Berghe
patent: 2-170725 (1990-07-01), None
patent: 6-260944 (1994-09-01), None
patent: 8-237145 (1996-09-01), None
patent: 0924702 (1997-09-01), None
Garrett et al., Low power architecture of soft-output Viterbi algorithm, 1998, University of VA, p. 1 to 6.

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