Low power testing of very large circuits

Details Low power testing of very large circuits Low power testing of very large circuits

2009-12-15

2010-10-26

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S727000

Reexamination Certificate

active

07823036

ABSTRACT:
Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

REFERENCES:
patent: 5428622 (1995-06-01), Kuban et al.
patent: 6041176 (2000-03-01), Shiell
patent: 6158032 (2000-12-01), Currier et al.
patent: 6304099 (2001-10-01), Tang et al.
patent: 6327685 (2001-12-01), Koprowski et al.
patent: 6594802 (2003-07-01), Ricchetti et al.
Chakravarty, S.; Dabholkar, V.P.; , “Two techniques for minimizing power dissipation in scan circuits during test application,” Test Symposium, 1994., Proceedings of the Third Asian , vol., No., pp. 324-329, Nov. 15-17, 1994 doi: 10.1109/ATS.1994.367211 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=367211&isnumber=8409.
Dabholkar, V.; Chakravarty, S.; Pomeranz, I.; Reddy, S.; , “Techniques for minimizing power dissipation in scan and combinational circuits during test application,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol. 17, No. 12, pp. 1325-1333, Dec. 1998doi: 10.1109/43.736572 URL: http://ieeexplore.ieee.org/stamp/stamp.
Stroele, A.P.; , “Reducing BIST hardware by test schedule optimization,” Test Symposium, 1992. (ATS '92), Proceedings., First Asian (Cat. No. TH0458-0) , vol., No., pp. 253-258, Nov. 26-27, 1992 doi: 10.1109/ATS.1992.224399 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=224399&isnumber=5869.
“IEEE Standard Test Access Port and Boundary—Scan Architecture,” IEEE Std 1149.1-1990 , vol., No., pp. 0—1, 1990 doi: 10.1109/IEEESTD.1990.114395 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=211226&isnumber=5509.

Affiliated with

Also associated with

Rating

Low power testing of very large circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power testing of very large circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power testing of very large circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4232316