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Gaining access to internal nodes in a PLD

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Galios field processor having dual parallel data path for...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Galois field computation system and method

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Galois field multiply accumulator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Gaming apparatus having memory fault detection

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Gaming machine having game play suspension and resumption...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Gaming machine with power-hit tolerant data storage

Error detection/correction and fault detection/recovery – Data processing system error or fault handling
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Gap detector detecting gaps between transactions transmitted...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Gate close balking for fair gating in a nonuniform memory...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Gate close failure notification for fair gating in a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Gating circuitry coupling selected scan paths between I/O...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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GBit/s transceiver with built-in self test features

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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General port capable of implementing the JTAG protocol

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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General Purpose Interface Bus (GPIB) system and method which pro

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Generalized address generation for bit reversed random...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Generalized convolutional interleaver/de-interleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Generalized convolutional interleaver/deinterleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Generalized convolutional interleaver/deinterleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Generalized convolutional interleaver/deinterleaver

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
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Generalized fault model for defects and circuit marginalities

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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