Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-02-21
2006-02-21
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S785000
Reexamination Certificate
active
07003715
ABSTRACT:
An OC-192 front-end application-specific integrated circuit (ASIC) de-interleaves an OC-192 signal to create four OC-48 signals, and decodes error-correction codes embedded in each of the four OC-48 signals. The decoder generates a Bose-Chaudhuri-Hocquenghem (BCH) error polynomial in no more than 12 clock cycles. The decoder includes several Galois field multiply accumulators, and a state machine which controls the Galois field units. In the specific embodiment wherein the error-correction code is a BCH triple error-correcting code, four Galois field units are used to carry out only six equations to solve the error polynomial. The Galois field units are advantageously designed to complete a Galois field multiply/accumulate operation in a single clock cycle. The Galois field units may operate in multiply or addition pass-through modes.
REFERENCES:
patent: 4597083 (1986-06-01), Stenerson
patent: 4873688 (1989-10-01), Maki et al.
patent: 5051999 (1991-09-01), Erhart et al.
patent: 5363379 (1994-11-01), Eckenrode et al.
patent: 5574717 (1996-11-01), Tomizawa et al.
patent: 5583499 (1996-12-01), Oh et al.
patent: 5642367 (1997-06-01), Kao
patent: 5673279 (1997-09-01), Oskouy et al.
patent: 5710782 (1998-01-01), Weng
patent: 5818855 (1998-10-01), Foxcroft
patent: 6199188 (2001-03-01), Shen et al.
patent: 6286123 (2001-09-01), Kim
patent: 6385751 (2002-05-01), Wolf
patent: 6571368 (2003-05-01), Chen
patent: 6683855 (2004-01-01), Bordogna et al.
patent: 6684350 (2004-01-01), Theodoras, II et al.
patent: 6684364 (2004-01-01), Cameron
patent: 6751743 (2004-06-01), Theodoras, II et al.
patent: 2002/0165962 (2002-11-01), Alvarez et al.
Christian Schuler, “Code Generation Tools For Hardware Implementation Of FEC Circuits,” GMD FOKUS, Kaiserin-Augusta-Allee 31, 10589 Berlin, Germany.
Shu Lin and Daniel J. Costello, Jr., “Error Control CodingFundamentals and Applications,” Prentice-Hall, Inc. Englewood Cliffs, New Jersey, Chapter 6, pp. 141-183.
Campbell Stephenson Ascolese LLP
Cisco Technology Inc.
Ton David
LandOfFree
Galois field multiply accumulator does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Galois field multiply accumulator, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Galois field multiply accumulator will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3636946