Gating circuitry coupling selected scan paths between I/O...

Details Gating circuitry coupling selected scan paths between I/O... Gating circuitry coupling selected scan paths between I/O...

2010-12-13

2011-10-11

Chung, Phung M (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

08037383

ABSTRACT:
A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

REFERENCES:
patent: 5477545 (1995-12-01), Huang
patent: 6560734 (2003-05-01), Whetsel
patent: 6763488 (2004-07-01), Whetsel
patent: 7051257 (2006-05-01), Whetsel

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