GBit/s transceiver with built-in self test features

Details GBit/s transceiver with built-in self test features GBit/s transceiver with built-in self test features

2003-04-30

2008-03-04

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S733000

Reexamination Certificate

active

07340662

ABSTRACT:
GBit/s transceiver with built-in self test features. A method is disclosed for testing the operation of a transceiver having a digital processing section and an analog section, each having a transmit portion and a receive portion, the analog portions adaptable to interface with an analog network. The transceiver is first configured to operate in a test mode. In the test mode, the transmit portion of the digital processing section is activated to generate data to be transmitted by the transmit portion of the analog section. The receive portion of the analog section and the receive portion of the digital processing section are operated to receive data. Thereafter, the parametrics of select portions of the receive portion of the digital processing section are examined during the receipt of data by the receive portion of the analog section and processing thereof by the receive portion of the digital processing section.

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Antaki et al., Design for testability method for CML digital circuits, Jan. 1999, Proceedings of the conference on Design, automation and test in Europe DATE '99, Publisher: ACM Press.

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