Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2006-04-18
2006-04-18
Chung, Phung My (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S786000, C714S788000
Reexamination Certificate
active
07032138
ABSTRACT:
A memory-efficient convolutional interleaver/de-interleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.
REFERENCES:
patent: 5483541 (1996-01-01), Linsky
patent: 5572532 (1996-11-01), Fimoff et al.
patent: 6411654 (2002-06-01), Furutani et al.
Broadcom Corporation
Chung Phung My
Garlick Harrison & Markison LLP
Short Shayne X.
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