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Dynamic verification traversal strategies

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamic write cache size adjustment in raid controller with...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamic, Non-invasive detection of hot-pluggable problem...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically changing forward error correction and automatic requ

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Dynamically configurable debug port for concurrent support...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically configurable fault tolerance in autonomic...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically determining a buffer-stack overrun

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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Dynamically modifying parameters for servicing of storage...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically reconfigurable FPGA apparatus and method for multipr

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically reconfigurable interconnection

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable precision signal delay test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically reconfigurable shared scan-in test architecture

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Dynamically replacing a failed chip

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Dynamically tracking virtual logical storage units

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Dynamically-tunable memory controller

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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