Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1997-05-21
1999-08-03
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 11, 714774, 714797, G06F 1100, G06F 1108, H03M 1300
Patent
active
059319593
ABSTRACT:
Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote. The FPGA engine's flexibility extends to allowing for multiprocessing among the modules where the FPGA engine supports message passing. Implementing these functions in hardware instead of software makes them execute faster. The FPGA is reprogrammable, and only the functions required immediately need be implemented. Inactive functions are stored externally in a Read-Only Memory (ROM). The dynamically reconfigurable FPGA gives the fault-tolerant system an output stage that offers low gate complexity by storing the unused "gates" as configuration code in ROM. Lower gate complexity translates to a highly reliable output stage, prerequisite to a fault tolerant system.
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Proceedings Sixth IEEE International Workshop on Rapid System Prototyping, Jun. 1995, "Modeling a Versatile FPGA for Prototyping Adaptive Systems", Kevin A. Kwiat, Warren H. Debany, Jr., Salim Hariri, pp. 174-180.
Proceedings Sixth Great Lakes Symposium on VLSI(IEEE), Jul. 1996, "Software Fault Tolerance Using Dynamically Reconfigurable FPGAs", Kevin A. Kwiat, Warren H. Debany, Jr., Salim Hariri, pp. 39-42.
Proceedings of the Third ISSAT International Conference on Reliability and Quality in Design, Mar. 1997, ISBN:0-9639998-2-6, Kevin A. Kwiat, Warren Debany, Salim Hariri, pp. 145-149, "Fault Tolerant and High Performance Computing with Dynamically Reconfigurable FPGAs" (Title).
Beausoliel, Jr. Robert W.
Burstyn Harold L.
Shaw Brian H.
The United States of America as represented by the Secretary of
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