Update scheme for impedance controlled I/O buffers
Updating configuration for programmable logic device
Upgradeable and reconfigurable programmable logic device
Upgradeable and reconfigurable programmable logic device
Upward and downward pulse stretcher circuits and modules
USB 1.1 for USB OTG implementation
USB 2.0 HS voltage-mode transmitter with tuned termination...
USB 2.0 HS voltage-mode transmitter with tuned termination...
USB device and data processing system having the same
Use of dangling partial lines for interfacing in a PLD
Use of dangling partial lines for interfacing in a PLD
Use of dual hysteresis modes in determining a loss of signal...
Use of molecular electrostatic potential to process...
User configurable on-chip memory system
User programmable product term width expander
User-accessible freeze-logic for dynamic power reduction and...
User-accessible freeze-logic for dynamic power reduction and...
User-configurable logic circuits comprising antifuses and multip
Users registers in a reconfigurable IC
Using a single buffer for multiple I/O standards