Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Patent
1996-04-04
1998-05-12
Westin, Edward P.
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
326 87, 326 50, H03K 1716
Patent
active
057511616
ABSTRACT:
A method and circuit are disclosed for changing the output impedance of an impedance controlled buffer from an initial impedance to a final impedance, while minimizing data transmission errors. The buffer has a plurality of impedance control inputs, with each of the plurality of impedance control inputs receiving a corresponding one of a plurality of bits of a binary coded impedance control signal. The output impedance of the buffer is controlled as a function of a value of the impedance control signal. First, the value of the impedance control signal is changed from an initial value corresponding to the initial output impedance to an intermediate value corresponding to an intermediate output impedance which is less than the initial output impedance. Next, the intermediate value of the impedance control signal is changed to a final value corresponding to the final output impedance.
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Bach Randall
Wei Shuran
Driscoll Benjamin D.
LSI Logic Corporation
Westin Edward P.
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