Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2001-09-07
2002-12-03
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C327S205000, C326S021000
Reexamination Certificate
active
06489803
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuits used in communication systems and more particularly to determining loss of signal conditions associated therewith.
2. Description of the Related Art
Interruptions occur in data transmission for a variety of reasons such as equipment failure, a cut cable or excessive attenuation of the signal. When such an interruption occurs, it is typical for the intended receiver in the data transmission system to detect the failure condition and inform the communication system of the existence of the failure. Many communication systems specify various aspects of detecting such loss of signal (LOS) conditions. For example, the Synchronous Optical Network (SONET) specification requires that LOS be raised when the synchronous signal (STS-N) level drops below the threshold at which a bit error rate (BER) of 1×10
−3
is predicted.
A clock and data recovery circuit operating in such a communication system typically receives the input data stream as a differential signal. One approach to detecting loss of signal conditions has been to rectify the received signal and compare the received signal to a reference level. Peak detection has also been used. However, such loss of signal techniques has been typically implemented in bipolar technologies. Their implementation in CMOS technologies is difficult. Since it may be desirable to implement various designs in CMOS from cost and ease of manufacturing as well as for power and performance reasons, it would be desirable to have a loss of signal approach that could be implemented in CMOS.
One aspect of detecting a loss of signal condition is to provide an indication of the existence of such a condition. It would be desirable to provide improvements in supplying that loss of signal indication.
SUMMARY OF THE INVENTION
Accordingly, the invention relates to utilization of hysteresis in determining whether a loss of signal condition exists for an input data stream. The use of hysteresis prevents the indication of a loss of signal condition from changing too frequently when the signal strength of the input data stream is close to the signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. The LOS threshold level may be supplied, e.g., on an input terminal of the integrated circuit. For certain LOS threshold levels, hysteresis proportional to the signal strength threshold level may be sufficient. In such circumstances, e.g., the hysteresis utilized in deasserting a loss of signal indication is 3 db of the signal strength threshold. Thus, for example, a 20 mV peak-to-peak signal strength level for assertion would have a 30 mV peak-to-peak level for deassertion. However, at low signal strength thresholds, e.g., 6 mV, 3 db of hysteresis may not be sufficient given the magnitude of noise and other factors. Accordingly, a fixed amount of hysteresis is used for low signal strength thresholds in order to ensure-that the hysteresis level is sufficient.
In one embodiment a method is provided for determining whether a loss of signal condition exists for an input data stream according to a signal strength threshold level. The signal strength threshold level is determined according to a supplied loss of signal (LOS) threshold level. The method uses hysteresis for the signal strength threshold level that is proportional to the LOS threshold level when the LOS threshold level is above a predetermined level and uses fixed hysteresis for the signal strength threshold level when the LOS threshold level is below the predetermined level. The hysteresis provides a signal strength threshold level that has a greater magnitude on deassertion of a loss of signal indication than on assertion of the loss of signal indication. In one embodiment the fixed hysteresis amount is provided digitally.
In another embodiment an integrated circuit is provided that includes a first hysteresis circuit coupled to receive a loss of signal (LOS) threshold indication and to supply first and second loss of signal threshold (LOS) signals, the first LOS threshold signal threshold signal being proportionally larger than the second LOS threshold signal, thus providing hysteresis in proportion to the LOS threshold indication. A second hysteresis circuit provides a signal with a fixed hysteresis amount relative to the LOS threshold indication. A control circuit selects either the hysteresis in proportion to the LOS signal or the fixed hysteresis based on the level of the LOS threshold indication.
In still another embodiment, an integrated circuit includes a hysteresis mode circuit coupled to compare a threshold signal indicative of a threshold level to a predetermined value and to indicate a first hysteresis mode when the threshold signal is above the predetermined value and to indicate a second hysteresis mode when the threshold signal is below the predetermined value. A first hysteresis circuit supplies hysteresis proportional to the threshold level in the first hysteresis mode. A second hysteresis circuit supplies fixed hysteresis with respect to the threshold level in the second hysteresis mode.
REFERENCES:
patent: 5930721 (1999-07-01), Fried et al.
Pepenella Gerard
Steiner Philip David
Le Don Phu
Silicon Laboratories Inc.
Zagorin O'Brien & Graham LLP
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