Structures and methods for avoiding hold time violations in...
Structures and methods for distributing high-fanout signals...
Structures and methods for implementing ternary...
Structures and methods for reducing power consumption in...
Structures and methods for selectively applying a well bias...
Structures and methods for testing programmable logic...
Structures and methods of implementing a pass gate...
Structures and methods of testing interconnect structures in...
Structures and methods providing columns of tightly coupled...
Structures and methods providing columns of tightly coupled...
Structures and methods to avoiding hold time violations in a...
Sub-cycle configurable hybrid logic/interconnect circuit
Super VCC detection circuit
Supply voltage independent ramp-up circuit
Swap MUX to relieve logic device input line stress
Switch block and corresponding switch matrix, in particular...
Switch matrices using reduced number of switching devices for si
Switch matrix circuit, logical operation circuit, and switch...
Switch matrix circuit, logical operation circuit, and switch...
Switching circuits and methods for programmable logic devices