Switching circuits and methods for programmable logic devices

Details Switching circuits and methods for programmable logic devices Switching circuits and methods for programmable logic devices

2007-08-03

2009-12-08

Cho, James (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S040000

Reexamination Certificate

active

07629812

ABSTRACT:
A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line to a second signal line and include one or more switch junction field effect transistors (JFETs) having a first control gate separated from a second control gate by a channel region.

REFERENCES:
patent: 3412286 (1968-11-01), Grebene
patent: 3930300 (1976-01-01), Nicolay
patent: 3951702 (1976-04-01), Kano et al.
patent: 3955182 (1976-05-01), Bert
patent: 3967305 (1976-06-01), Zuleeg
patent: RE28905 (1976-07-01), Hodges
patent: 4064525 (1977-12-01), Kano et al.
patent: 4126900 (1978-11-01), Koomen et al.
patent: 4207556 (1980-06-01), Sugiyama et al.
patent: 4228367 (1980-10-01), Brown
patent: 4333224 (1982-06-01), Buchanan
patent: 4485392 (1984-11-01), Singer
patent: 4516040 (1985-05-01), Zapisek et al.
patent: 4613772 (1986-09-01), Young
patent: 4631426 (1986-12-01), Nelson et al.
patent: 4663543 (1987-05-01), Sitch
patent: 4698653 (1987-10-01), Cardwell, Jr.
patent: 4743862 (1988-05-01), Scheinberg
patent: 4751556 (1988-06-01), Cogan et al.
patent: 4777517 (1988-10-01), Onodera et al.
patent: 4853561 (1989-08-01), Gravrok
patent: 4985739 (1991-01-01), Lapham et al.
patent: 5130770 (1992-07-01), Blanc et al.
patent: RE34363 (1993-08-01), Freeman
patent: 5408198 (1995-04-01), Kusunoki
patent: 5618688 (1997-04-01), Reuss
patent: 5764096 (1998-06-01), Lipp et al.
patent: 5773891 (1998-06-01), Delgado
patent: 5808502 (1998-09-01), Hui et al.
patent: 5973341 (1999-10-01), Letavic et al.
patent: 6307223 (2001-10-01), Yu
patent: 6781409 (2004-08-01), Turner
patent: 6940307 (2005-09-01), Liu et al.
patent: 7141853 (2006-11-01), Campbell et al.
patent: 7307445 (2007-12-01), Liang et al.
patent: 2002/0197779 (2002-12-01), Evans
patent: 2007/0008013 (2007-01-01), Fijany et al.
patent: 2007/0096144 (2007-05-01), Kapoor
patent: 2007/0126478 (2007-06-01), Kapoor
patent: 2007/0284628 (2007-12-01), Kapoor
patent: 0193842 (1986-09-01), None
patent: 0 276 760 (1988-08-01), None
patent: 1268175 (1972-03-01), None
patent: 2208967 (1989-04-01), None
patent: 59 061317 (1984-04-01), None
patent: 60-258948 (1985-12-01), None
patent: 60258948 (1985-12-01), None
patent: 7 203 662 (1972-09-01), None
U.S. Appl. No. 11/796,434, Not Published, Vora.
Hamadė, Adib R., “A JFET/Bipolar Eight-Channel Analog Multiplexer”,IEEE Journal of Solid-State Circuits, Dec. 1975, pp. 399-406, vol. SC-10, No. 6.
Takagi et al., “Complementary JFET Negative-Resistance Devices”,IEEE Journal of Solid-State Circuits, Dec. 1975, pp. 509-515, vol. SC-10, No. 6.
Lehovec, Kurt, “Analysis of GaAs FET's for Integrated Logic”,IEEE Transactions on Electron Devices, Jun. 1980, pp. 1074-1091, vol. ED-27, No. 6.
Ozawa, Osuma, “Electrical Properties of a Triode-Like Silicon Vertical-Channel JFET”,IEEE Transactions on Electron Devices, Nov. 1980, pp. 2115-2123, vol. ED-27, No. 11.
Nanver et al., “Design Considerations for Integrated High-Frequency p-Channel JFET's”,IEEE Transactions on Electron Devices, Nov. 1988, pp. 1924-1934, Vol. 35, No. 11.
Moulic, J., “Field Effect Transistor Shifted Logic”,IBM Technical Disclosure Bulletin, vol. 33, No. 3A, Aug. 1990, pp. 343-346.
PCT International Search Report and Written Opinion of the International Searching Authority for International Application, PCT/US2007/071075, dated Apr. 25, 2008.
English Abstract of JP 59 061317 from the European Patent Office.
Kuon, Ian Carlos, “Automated FPGA Design, Verification and Layout” Thesis for Degree of Master of Applied Science, Graduate Department of Electrical and Computer Engineering, University of Toronto, 2004, p. 71.
Muggli, R.A., “Double Gate Bipolar Compatible N-Channel Junction FET”,IBM Technical Disclosure Bulletin, vol. 24, No. 2, Jul. 1981, pp. 997-998.
Wong, W. W. et al., “A Unified Four-Terminal JFET Static Model for Circuit Simulation”,Solid-State Electronics, vol. 34, No. 5, pp. 437-443, 1991.
PCT International Search Report and Written Opinion of the International Search Authority for International Application No. PCT/US2008/071338, dated Nov. 18, 2008.

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