Sub-cycle configurable hybrid logic/interconnect circuit

Details Sub-cycle configurable hybrid logic/interconnect circuit Sub-cycle configurable hybrid logic/interconnect circuit

2007-12-11

2007-12-11

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S041000

Reexamination Certificate

active

11269168

ABSTRACT:
Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

REFERENCES:
patent: 4873459 (1989-10-01), El Gamal et al.
patent: 5245575 (1993-09-01), Sasaki et al.
patent: 5349250 (1994-09-01), New
patent: 5357153 (1994-10-01), Chiang et al.
patent: 5365125 (1994-11-01), Goetting et al.
patent: 5369622 (1994-11-01), McLaury
patent: 5426378 (1995-06-01), Ong
patent: 5521835 (1996-05-01), Trimberger
patent: 5532958 (1996-07-01), Jiang et al.
patent: 5552721 (1996-09-01), Gould
patent: 5610829 (1997-03-01), Trimberger
patent: 5631578 (1997-05-01), Clinton et al.
patent: 5646544 (1997-07-01), Iadanza
patent: 5659484 (1997-08-01), Bennett et al.
patent: 5682107 (1997-10-01), Tavana et al.
patent: 5692147 (1997-11-01), Larsen et al.
patent: 5694057 (1997-12-01), Gould
patent: 5719889 (1998-02-01), Iadanza
patent: 5732246 (1998-03-01), Gould et al.
patent: 5737235 (1998-04-01), Kean et al.
patent: 5745422 (1998-04-01), Iadanza
patent: 5745734 (1998-04-01), Craft et al.
patent: 5764954 (1998-06-01), Fuller et al.
patent: 5768178 (1998-06-01), McLaury
patent: 5777360 (1998-07-01), Rostoker et al.
patent: 5802003 (1998-09-01), Iadanza et al.
patent: 5815726 (1998-09-01), Cliff
patent: 5889411 (1999-03-01), Chaudhary
patent: 5914616 (1999-06-01), Young et al.
patent: 5914906 (1999-06-01), Iadanza et al.
patent: 5982655 (1999-11-01), Doyle
patent: 6002991 (1999-12-01), Conn, Jr.
patent: 6023421 (2000-02-01), Clinton et al.
patent: 6038192 (2000-03-01), Clinton et al.
patent: 6044031 (2000-03-01), Iadanza et al.
patent: 6054873 (2000-04-01), Laramie
patent: 6069490 (2000-05-01), Ochotta et al.
patent: 6075745 (2000-06-01), Gould et al.
patent: 6086631 (2000-07-01), Chaudhary et al.
patent: 6091263 (2000-07-01), New et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6107821 (2000-08-01), Kelem et al.
patent: 6110223 (2000-08-01), Southgate et al.
patent: 6118707 (2000-09-01), Gould et al.
patent: 6130854 (2000-10-01), Gould et al.
patent: 6134154 (2000-10-01), Iwaki et al.
patent: 6140839 (2000-10-01), Kaviani et al.
patent: 6150838 (2000-11-01), Wittig et al.
patent: 6163168 (2000-12-01), Nguyen et al.
patent: 6173379 (2001-01-01), Poplingher et al.
patent: 6175247 (2001-01-01), Scalera et al.
patent: 6184707 (2001-02-01), Norman et al.
patent: 6205076 (2001-03-01), Wakayama
patent: 6233191 (2001-05-01), Gould et al.
patent: 6275064 (2001-08-01), Agrawal et al.
patent: 6292019 (2001-09-01), New et al.
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6346824 (2002-02-01), New
patent: 6348813 (2002-02-01), Agrawal et al.
patent: 6381732 (2002-04-01), Burnham et al.
patent: 6469540 (2002-10-01), Nakaya
patent: 6487709 (2002-11-01), Keller et al.
patent: 6490707 (2002-12-01), Baxter
patent: 6496918 (2002-12-01), Dehon et al.
patent: 6515509 (2003-02-01), Baxter
patent: 6526559 (2003-02-01), Schiefele et al.
patent: 6529040 (2003-03-01), Carberry et al.
patent: 6545501 (2003-04-01), Bailis et al.
patent: 6593771 (2003-07-01), Bailis et al.
patent: 6601227 (2003-07-01), Trimberger
patent: 6603330 (2003-08-01), Snyder
patent: 6629308 (2003-09-01), Baxter
patent: 6636070 (2003-10-01), Altaf
patent: 6642744 (2003-11-01), Or-Bach et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6668361 (2003-12-01), Bailis et al.
patent: 6675309 (2004-01-01), Baxter
patent: 6714041 (2004-03-01), Darling et al.
patent: 6732068 (2004-05-01), Sample et al.
patent: 6806730 (2004-10-01), Bailis et al.
patent: 6809979 (2004-10-01), Tang
patent: 6831479 (2004-12-01), Lo
patent: 6838902 (2005-01-01), Elftmann et al.
patent: 6924663 (2005-08-01), Masui et al.
patent: 6937535 (2005-08-01), Ahn et al.
patent: 6956399 (2005-10-01), Bauer
patent: 6992505 (2006-01-01), Zhou
patent: 6998872 (2006-02-01), Chirania et al.
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7075333 (2006-07-01), Chaudhary et al.
patent: 7126372 (2006-10-01), Vadi et al.
patent: 7126856 (2006-10-01), Sun et al.
patent: 7129746 (2006-10-01), Balasubramanian et al.
patent: 2001/0007428 (2001-07-01), Young et al.
patent: 2002/0008541 (2002-01-01), Young et al.
patent: 2002/0113619 (2002-08-01), Wong
patent: 2002/0125910 (2002-09-01), New et al.
patent: 2002/0125914 (2002-09-01), Kim
patent: 2002/0161568 (2002-10-01), Sample et al.
patent: 2002/0163357 (2002-11-01), Ting
patent: 2003/0042931 (2003-03-01), Ting
patent: 2003/0080777 (2003-05-01), Baxter
patent: 2003/0110430 (2003-06-01), Bailis et al.
patent: 2004/0010767 (2004-01-01), Agrawal et al.
patent: 2004/0103265 (2004-05-01), Smith
patent: 2004/0196066 (2004-10-01), Ting
patent: 2004/0233758 (2004-11-01), Kim et al.
patent: 2005/0146352 (2005-07-01), Madurawe
“§3 Programmable Logic Devices,”Digital System Design, 2001 Month N/A, pp. 3.1-3.28.
“The Effect of SRAM Table Sharing and Cluster Size on FPGA Area”, NPL Date Unknown, pp. 1-10.
“Unifying Sequential and Spatial Computing with a Single Instruction Set Architecture,”ISCA '04, Jun. 19-23, 2004, ACM, Munchen, Oberbayern, Germany.
Agrawal, O., et al., “An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-gating Functions,”FPGA 99, Feb. 1999, pp. 17-26, ACM, Monterey, California, USA.
Ahmed, E., et al., “The Effect of LUT and Cluster Size on Deep-Submicron FPGA Performance and Density,”FPGA 2000, Feb. 2000, ACM, Monterey, California, USA.
Barker, R., “QuickSilver ACM SilverStream Design Methodology with the Inspire SDK Tool Set ,”A Technology Application Whitepaper, Jan. 26, 2004, pp. 1-8, QuickSilver Technology, Inc., San Jose, California, USA.
Butts, M., “Future Directions of Dynamically Reprogrammable Systems,”IEEE 1995 Custom Integrated Circuits Conference, May 1995, pp. 487-494, IEEE.
Camposano, R., “The Growing Semiconductor Zoo: ASICs, CSSP, ASSp, ASIP, Structured Arrays, FPGAs, Processor Arrays, Platforms . . . and Other Animalia,” Aug. 29, 2003, pp. 1-74, Synopsys, Inc.
Compton, K. et al., “An Introduction to Recconfigurable Computing,”IEEE Computer, Apr. 2000.
Cong, J., et al., “A Theory on Partially-Dependent Functional Decomposition with Application in LUT-based FPGA,” 1995 Month N/A, pp. 1-22.
Coudert, O., “Chapter 13: Doing Two-Level Logic Minimization 100 Times Faster,”Proceedings of the 6thAnnual ACM-SIAM Symposium on Discrete Algorithms, Jan. 1995, pp. 112-121.
Damiani, M., et al., “The Disjunctive Decomposition of Logic Functions,”Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, Nov. 1997, pp. 78-82, San Jose, California, USA.
Dehon, A., “Balancing Interconnect and Computation in a Reconfigurable Computing Array (or, why don't you really want 100% LUT utilization),”Proceedings of the International Symposium on Field Programmable Gate Arrays, Feb. 1999, pp. 125-134.
Dehon, A., “DPGA Utilization and Application,”Proceedings of the 1996 ACM Fourth International Symposium on Field-Programmable Gate Arrays FPGA, Feb. 11-13, 1996, Monterey, California, USA.
Dehon, A., et al., “DPGA-Coupled Microprocessors: Commodity ICs for the Early 21stCentury,”FCCM '94-IEEE Workshop on FPGAs for Custom Computing Machines, Apr. 1994, Napa Valley, California, USA.
Dehon, A., et al., “Reconfigurable Computing: What, Why, and Implications for Design Automation,”DAC 1999, Jun. 1999, ACM, New Orleans, Louisiana.
Enzler, R., et al., “Virtualizing Hardware with Multi-Context Recconfigurable Arrays,”Lecture Notes in Computer Science, Sep. 2003, pp. 151-160.
George, V., “Low Energy Field-Programmable Gate Array,”A Dissertation Submitted in Partial S

Affiliated with

Also associated with

Rating

Sub-cycle configurable hybrid logic/interconnect circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sub-cycle configurable hybrid logic/interconnect circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sub-cycle configurable hybrid logic/interconnect circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3847497