Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2001-12-18
2003-07-08
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S016000, C326S039000, C326S040000, C326S041000, C714S724000, C714S725000
Reexamination Certificate
active
06590416
ABSTRACT:
BACKGROUND
Complex programmable logic devices (CPLDs) are well-known integrated circuits that may be programmed to perform various logic functions. Numerous types of memory elements may be used in CPLD architectures to provide programmability. One such memory element, known as a flash memory cell, is both electrically programmable and erasable. Program and erase are performed on a plurality of flash memory cells using either Fowler-Nordheim tunneling or hot electron injection for programming and Fowler-Nordheim tunneling for erasing. Flash memories can also be in-system programmable (ISP). An ISP device can be programmed, erased, and can have its program state verified after it has been connected, such as by soldering, to a system printed circuit board. Some CPLDs do not have ISP capability and must be programmed externally (outside the system) by programming equipment.
Continuous advances in integrated-circuit process technology have dramatically reduced device feature size. The reduction in feature size improves device performance while at the same time reducing cost and power consumption. Unfortunately, smaller feature sizes also increase a circuit's vulnerability to over-voltage conditions. Among the more sensitive elements in a modern integrated circuit are the gate oxide layers of MOS transistors. These layers are very thin in modern devices, and are consequently easily ruptured by excessive voltage levels. Modern circuits with small feature sizes therefore employ significantly lower source voltages than was common only a few years ago. For example, modern 0.18-micron processes employ supply voltages no greater than 2 volts.
The voltages required to program and erase flash memory cells are dictated by physical properties of the materials used to fabricate memory cells. Unfortunately, these physical properties have not allowed the voltages required to program, erase, and verify the program state of a memory cell to be reduced in proportion to reductions in supply voltages. For example, modern flash memory cells adapted for use with a 0.18-micron processes require program and erase voltages as high as 14 volts, a level far exceeding the required 1.8-volt supply level. For a more detailed treatment of program, erase, and verify procedures, see U.S. Pat. No. 5,889,701, which is incorporated herein by reference.
FIG. 1
(prior art) depicts a conventional CPLD
100
. The circuitry within CPLD
100
is instantiated on an integrated circuit chip
105
, which is later wire bonded to pins
110
of a device package
115
using a number of bond wires
120
. Bond wires
120
connect to respective bond pads
125
, some of which extend to respective input/output circuits
130
. Input/output circuits
130
convey signals to and from other programmable logic and interconnect resources (not shown). The logic of input/output circuits
130
and these configurable elements is dictated by the program state of a collection of configuration memory cells
135
.
Integrated circuits, including CPLDs, undergo substantial test procedures. Among these tests, memory cells are programmed, erased, and their states verified to insure proper device operation. To accomplish this, a sophisticated test apparatus, or “tester,” applies and receives signals via pads on the integrated circuit. These pads might be bond pads, like bond pads
125
, or dedicated test pads used only to make contact with the tester.
Chip
105
depicts two test-specific pads
145
, sometimes called “octal pads,” connected to a ramp-up circuit
150
. A pair of test pins
155
extends from an external tester (not shown) to pads
145
to convey a relatively high programming voltage VPP and a control signal CTRLB to circuit
150
. Circuit
150
uses these two external test signals to develop a ramped version VPP_R of the programming voltage VPP to steering logic
160
. While VPP is referred to herein as a “programming” voltage, it is to be understood that the applied voltage on terminal VPP might also be used to erase memory cells. Moreover, as with other designations in the present disclosure, VPP refers to both the signal and the corresponding circuit node. Whether a given designation refers to a node or a signal will be clear from the context.
Steering logic
160
selectively applies the ramped up program voltage VPP_R to the bitlines of memory cells within the box labeled memory cells
135
. Though shown in
FIG. 1
as a discrete area, memory cells
135
are typically distributed throughout chip
105
to control the various programmable resources. A power line
165
conveys a power-supply voltage VDD from one of external supply pins
110
to I/O circuits
105
and the other internal components (not shown).
FIG. 2
(prior art) depicts a more detailed schematic of ramp-up circuit
150
of FIG.
1
. Ramp-up circuit
150
receives as input the relatively high programming voltage VPP on octal pad
145
. EEPROM cells can be damaged if programming and erase voltages are applied too quickly. Ramp-up circuit
150
is therefore provided to raise the external program or erase voltages on the respective pad
145
gradually to the appropriate voltage level.
Ramp-up circuit
150
includes a clock terminal
200
adapted to receive a clock signal generated either internally or externally to CPLD
100
. Control signal CTRLB is shown here associated with an octal pad
145
, but the control signal can also be generated internally, or can be received externally via a different type of pad. The last letter of the designation CTRLB indicates that the control signal is an active low (i.e., the B is for “bar”), and this convention is used throughout the present application.
The clock and control signals are fed into a circuit
205
that divides the clock signal into a pair of complimentary clocks C
1
and C
2
. These clocks are then each fed via respective capacitors to an output circuit
210
. Output circuit
210
receives the externally generated high-voltage signal VPP as an additional input, and also receives the compliment CTRL of control signal CTRLB.
When control signal CTRLB is brought low, output circuit
210
ramps up the voltage on the gate of a transistor
215
from zero volts to a level above VPP. The output VPP_R of ramp-up circuit
150
thus gently approaches the requisite program voltage VPP to be directed to the bit line of one or more memory cells. The output VPP_R ramps up over a time RT determined primarily by the clock signal CLK and the values of the capacitors between circuits
205
and
210
. The output VPP_R returns to zero when control signal CTRLB is brought high.
The trouble with ramp-up circuit
150
is that the voltage on the gate of transistor
215
must rise above the voltage level VPP. As noted above, modern integrated circuits are becoming ever more sensitive to high voltages, so it is beneficial to keep all voltages presented to CPLD
100
as low as possible.
SUMMARY
The present invention is directed to a ramp-up circuit that receives a relatively high program voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program voltage to provide a ramped up version of the programming signal to the memory cells. The gradual ramping of the program voltage prevents damage to the memory cells.
The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program voltage to the memory cells without raising internal circuit nodes above the program voltage. This aspect of the invention reduces the maximum voltage required on nodes within the circuit, and therefore protects sensitive components from potentially damaging over-voltage conditions.
This summary does not define the scope of the invention, which is instead defined by the appended claims.
REFERENCES:
patent: 5821771 (1998-10-01), Patel et al.
patent: 5889701 (1999-03-01), Kang et al.
patent: 6114843 (2000-09-01), Olah
patent: 6150835 (2000-11-01), Hazen et al.
patent: 6288526 (2001-09-01), Olah
Xilinx Advance Product Specification DS012 (v1.4) “CoolRunner XPLA3 CP
Davies, Jr. Thomas J.
Om'Mani Henry A.
Behiel Arthur J.
Tan Vibol
Tokar Michael
Xilinx , Inc.
Young Edel M.
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