Structures and methods for implementing ternary...

Details Structures and methods for implementing ternary... Structures and methods for implementing ternary...

2007-09-25

2007-09-25

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S039000, C326S040000

Reexamination Certificate

active

11373700

ABSTRACT:
Structures and methods of implementing an adder circuit in a programmable logic device (PLD). The PLD includes dual-output lookup tables (LUTs) and additional programmable logic elements. The adder circuit includes a 3:2 (3 to 2) compressor circuit that maps three input busses into two compressed busses, and a 2-input cascade adder circuit that adds the two compressed busses to yield the final sum bus. The dual-output LUTs implement both the 3:2 compressor circuit and a portion of the 2-input adder. The remaining portion of the 2-input adder is implemented using the additional programmable logic elements of the PLD. In some embodiments, the 3:2 compressor circuit is preceded by an M:3 compressor, which changes the 3-input adder into an M-input adder. In these embodiments, a second input bus is left-shifted with respect to the first input bus, and a third input busses is left-shifted with respect to the second input bus.

REFERENCES:
patent: 7167022 (2007-01-01), Schleicher et al.
patent: 2003/0028846 (2003-02-01), Garrett
Xilinx, Inc.; “XtremeDSP for Virtex-4 FPGAs User Guide”; UG073 (v2.1) Dec. 19, 2005; available from Xilinx, Inc. at http://direct.xilinx.com/bvdocs/userguides/ug073.pdf; pp. 1-130.

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