Methods of reducing power in programmable logic devices...
Methods of reducing power in programmable logic devices...
Microcontroller accessible macrocell
Microcontroller having a block of logic configurable to...
Microprocessor having an effective BiCMOS extra multiple input c
Microprocessor having high speed, low noise output buffers
Microprocessor with software switchable clock speed and drive st
Mixed voltage, multi-rail, high drive, low noise, adjustable sle
Modular interconnect circuitry for multi-channel transceiver...
Molecular field programmable gate array
Monolithically integrated programmable device having elementary
Multi-buffered configurable logic block output lines in a field
Multi-chip programmable logic device having configurable...
Multi-functional I/O buffers in a field programmable gate...
Multi-level routing architecture in a field programmable...
Multi-level routing architecture in a field programmable...
Multi-level routing architecture in a field programmable...
Multi-level routing structure for a programmable...
Multi-master multi-slave system bus in a field programmable...
Multi-port memory devices