Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-05-14
2001-02-13
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000
Reexamination Certificate
active
06188241
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the manufacture of digital integrated circuits, and more particularly to the fabrication of microcontrollers.
2. Description of the Relevant Art
A typical computer system includes a microprocessor secured within its own semiconductor device package and coupled to several separately-packaged support devices. The support devices form circuits which perform support functions including communication functions and memory interface functions. A microcontroller is an integrated circuit which incorporates a microprocessor core along with one or more support circuits on the same monolithic semiconductor substrate (i.e., chip). Computer systems which employ microcontrollers may thus be formed using fewer semiconductor devices. Advantages of such systems include lower fabrication costs and higher reliabilities. Microcontrollers find applications in industrial and commercial products including control systems, computer terminals, hand-held communications devices (e.g., cellular telephones), photocopier machines, facsimile machines, and hard disk drives.
During manufacture of an integrated circuit (e.g., a microcontroller), signal lines formed upon the silicon substrate which are to be connected to external devices are terminated at flat metal contact regions called input/output (I/O) pads. The I/O pads are typically arranged about the periphery of the chip. Following manufacture, the integrated circuit is typically secured within a protective semiconductor device package. Each I/O pad of the chip is then connected to a terminal of the device package. The I/O pads of the chip are typically attached to the terminals of the device package by fine metal wires. Some types of device packages have terminals called “pins” for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a PCB.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more functions onto single silicon substrates. As the number of functions on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well, as do the complexities and costs of the device packages. As there are practical lower limits to the sizes of and distances between device package terminals, the sizes of device packages having hundreds of terminals are largely proportional to the required number of terminals. PCBs having multiple layers of closely-spaced conductive traces are required to accommodate such device packages. Attaching such device packages to PCBs also requires special tools and skills. Thus although increased integration reduces the manufacturing costs of integrated circuits, the costs of manufacturing systems which employ such integrated circuits often increase.
In an effort to reduce integrated circuit and system manufacturing costs, integrated circuit manufacturers are always looking for ways to reduce the number of required device package terminals. One common method of reducing the number of required device package terminals is to have two or more functions share selected device package terminals where possible.
FIG. 1
is a block diagram of a microcontroller
10
which employs such a device package terminal sharing (i.e., multiplexing) approach. Microcontroller
10
includes a first logic network
12
and a second logic network
14
coupled to an internal bus
16
. First logic network
12
and second logic network
14
share a set of I/O pads
18
via select logic
20
. Select logic
20
is coupled to first logic network
12
, second logic network
14
, internal bus
16
, and I/O pads
18
, and includes signal multiplexing and buffering circuitry. In response to control signals received via internal bus
16
, select logic
20
connects signal lines from either first logic network
12
or second logic network
14
to I/O pads
18
. First logic network
12
may be, for example, a liquid crystal display (LCD) driver circuit. Second logic network
14
may be, for example, a Video Electronics Standards Association (VESA) local bus (i.e., VL bus) controller. When an LCD display device is coupled to I/O pads
18
, microcontroller
10
is initialized with first logic network
12
(i.e., the LCD display driver circuit) enabled and second logic network
14
(i.e., the VL bus controller circuit) disabled. Select logic
20
couples signal lines from first logic network
12
to I/O pads
18
in order to control the LCD display device. When I/O pads
18
are coupled to the VL bus, microcontroller
10
is initialized with second logic network
14
enabled and first logic network
12
disabled. Select logic
20
couples signal lines from second logic network
14
to I/O pads
18
in order to allow microcontroller
10
to communicate with a peripheral device is coupled to the VL bus.
Programmable logic devices (PLDs) are commonly used to implement logic networks. PLDs are general-purpose digital components which are manufactured in an “unprogrammed” state, and are later “programmed” to implement a desired logical function. A PLD is typically programmed by a sequence of electrical pulses which configure one or more arrays of programmable switching elements within the PLD. Examples of different types of PLDs include programmable read-only memories (PROMs), field programmable logic arrays (FPLAs), programmable array logic devices (PALs), and field programmable gate arrays (FPGAs). A PROM with m inputs (i.e., address inputs) and n outputs (i.e., data outputs) can be configured to perform any m-input, n-output combinational logic function. FPLAs and PALs have AND and OR arrays. The AND array performs logical AND operations upon input values and their complements, forming product terms. The OR array performs logical OR operations upon the product terms, forming output values. The AND and OR arrays of FPLAs include programmable switching elements, while only the AND arrays of PALs are programmable. FPLAs and PALs implement combinational logic functions as a sum of the product terms (i.e., a sum of products) of input values. FPGAs are semi-custom logic devices including “islands” of programmable logic blocks called “logic cells” surrounded by an interconnection network which includes programmable switching elements. The logical functions performed by the logic cells are determined by programming, as are the interconnections formed between the logic cells. FPLAs, PALs, and FPGAs may also include storage elements (e.g., flip-flops) needed to implement sequential logic circuits.
All but one of the logic networks sharing a single set of I/O pads as described above are typically inactive at any given time. Such inactive logic networks occupy valuable chip area which could be used to implement other functions. It would thus be desirable to replace two or more logic networks which share a common set of I/O pads and the associated select logic with a single PLD capable of being configured to perform the desired logic function.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a microcontroller having a block of logic configurable to perform a selected logic function and to produce output signals coupled to corresponding I/O pads according to a predefined hardware interface. The microcontroller includes a central processing unit (CPU), a first set of I/O pads, and a configurable logic block (CLB) all formed upon a single monolithic semiconductor substrate. The CPU is configured to execute instructions, preferably x86 instructions. The CPU produces CPU output signals during instruction execution. The CLB is coupled between the CPU output signals and the first set of I/O pads. The CLB is configurable to perform a logic function selected from a predefined set of logic functions. Each member of the set of logic functions has an associated
Gauthier Lloyd W.
Hayat Faheem
Tobias David F.
Wakeland Carl K.
Advanced Micro Devices , Inc.
Conley Rose & Tayon
Daffer Kevin L.
Lam David
Nelms David
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