Methods of reducing power in programmable logic devices...

Details Methods of reducing power in programmable logic devices... Methods of reducing power in programmable logic devices...

2007-07-25

2009-12-29

Cho, James (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S068000

Reexamination Certificate

active

07639042

ABSTRACT:
Reduced voltage swing signal path circuitry is provided that lowers the internal signaling power consumption of the interconnection resources of a programmable logic device. The reduced voltage swing signal path circuitry includes a reversed routing driver circuitry to limit the voltage range of the output signal of the driver circuitry.

REFERENCES:
patent: 5187392 (1993-02-01), Allen
patent: 5525917 (1996-06-01), Wong et al.
patent: 5644255 (1997-07-01), Taylor
patent: 5818261 (1998-10-01), Perner
patent: 5909126 (1999-06-01), Cliff et al.
patent: 5963049 (1999-10-01), Cliff et al.
patent: 7088140 (2006-08-01), Nguyen et al.
patent: 2002/0024374 (2002-02-01), Ovens et al.
patent: 2004/0135147 (2004-07-01), Kim et al.
patent: 2006/0059837 (2006-03-01), Ahn et al.
patent: 0823786 (1998-02-01), None
patent: 1 605 511 (2005-12-01), None
patent: WO 2004/092816 (2004-10-01), None

Affiliated with

Also associated with

Rating

Methods of reducing power in programmable logic devices... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods of reducing power in programmable logic devices..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of reducing power in programmable logic devices... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4096029