Multi-level routing architecture in a field programmable...

Details Multi-level routing architecture in a field programmable... Multi-level routing architecture in a field programmable...

2006-09-13

2008-10-07

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S041000

Reexamination Certificate

active

07432733

ABSTRACT:
A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.

REFERENCES:
patent: 5381058 (1995-01-01), Britton et al.
patent: 6946871 (2005-09-01), Kundu et al.
patent: 7126374 (2006-10-01), Kundu et al.

Affiliated with

Also associated with

Rating

Multi-level routing architecture in a field programmable... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multi-level routing architecture in a field programmable..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multi-level routing architecture in a field programmable... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4001764