Molecular field programmable gate array

Details Molecular field programmable gate array Molecular field programmable gate array

1999-09-01

2001-04-10

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S010000

Reexamination Certificate

active

06215327

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to field programmable gate array circuits used in digital circuit design, and in particular, to an architectural design for their implementation on a molecular level.
2. Description of the Prior Art
This description outlines the prior practices in digital systems design and the construction of the gate array forms of integrated circuits.
A wide class of digital circuitry, referred to as clocked-mode (synchronous) digital systems, can be represented in a form shown in FIG.
1
. Any clocked-mode system can be represented as a “block” of combinational logic and a linear array of registers. Combinational logic makes binary (“0” or “1”) decisions based on Boolean functions of binary inputs and is the generalization of combinations of simple logic gates having one or two inputs (e.g., “AND”, “OR”, etc.) to a “block” of potentially many logic gates that inter-relate m inputs and n outputs. Even as a two-input “AND” gate relates a nearly trivial configuration of m=2 inputs and n=1 output, a generalized combinational logic block might have hundreds or more inputs and outputs.
The second part of a clocked-mode digital system, a linear array of registers, is equivalent in this representation to a set of data (“D”) flip-flops with a single, common clock input. The data inputs to the array of registers come from each of the n outputs of the combinational logic block. The outputs of these registers are then either: (1) outputs (y(t)) of the digital circuitry block, or (2) inputs that are “fed” back (quantity of r signals) into the combinational logic block (h(t)). The registers synchronize the overall operation of a clocked-mode digital system by permitting a change in the outputs only in relation to a single clock. This feature of synchronization is important since it is minimizes perturbations, especially in the inputs that are “fed” back into the combinational logic circuitry (eliminating the so-called “race” conditions). This approach to digital design is popular, predictable (easily modeled), and well-suited to automatic design methods, because when exploited properly, it creates circuitry with completely deterministic behavior.
In other digital systems representations and design approaches (referred to as asynchronous digital systems), the need for such synchronization is relaxed, albeit with considerably more involved design and analysis. The class of asynchronous systems can be shown to be the most general digital representation, and clocked-mode representations are a subset of asynchronous systems. In asynchronous systems, the lack of synchronizing/latching structures like registers and flip-flops make designs much more complex, and sometimes the feedback paths that give rise to sequential behavior become sensitive to process and circuit layout particulars that may escape less careful analyses. Mismatches in timing of paths within a circuit can create the well known hazard and “race” conditions where undesired transitions occur based on skewed information delivery to decision points within the circuitry. Most of the present invention is based on a synchronous model, but templates will also be discussed that can support a rich variety of asynchronous interactions as well.
The clocked-mode of representation is the basis of most digital circuitry today, to include finite state machines, micro-sequencers, central processing units, and many custom designs. As most of the automated synthesis of contemporary digital systems designs is based on clocked-mode representations and since many field programmable gate arrays are intended for this mode of operation, this restriction does not significantly limit utility of the present invention. The key restriction to the application of clocked-mode circuitry is the existence of a single “synchronization domain”, i.e., a single common clock controls the actions of the register array.
Very complex circuits contain multiple synchronization domains. It is not uncommon to divide very complex digital designs into synchronous and asynchronous sections, in which cases the synchronous content is usually dominant and lends itself to automatic design approaches. A full discussion of the ad hoc processes for multi-domain and asynchronous digital design are considerably involved and only have referential pertinence to the present invention. It is sufficient to indicate that the core concept of the present invention is based on approaches applicable to a single or a small number of synchronization domain(s) of a complex clocked-mode circuit. Asynchronous circuits can of course be more complex, since the synchronization domains may be ad hoc and in fact may be difficult to ascertain, which is among many of the reasons why asynchronous design is more complex and less represented in automated design approaches.
The role of storage and feedback in digital systems is necessary in order to implement stable and history-dependent behavior in a circuit. Combinational circuitry acts on the immediate values of input variables, which when changed or removed, can create a change in the output function. Changes in an output of a block of combinational logic are therefore subject to variations in the inputs. They are also subject to delays in the time responsiveness of the combinational circuitry itself, a real world effect which is largely due to the speed of signal propagation in circuit elements and the sluggishness of the circuitry to sudden changes (due to, for example, capacitive effects). Since digital systems need to rely on stable information, it is important that a decision based on the output of a combinational block be made after all delay effects have subsided. For this reason, the use of a register array is important, because it represents a snapshot in time of what should be the correct output of the combination circuitry. After the snapshot is taken, the inputs of the preceding combinational circuitry can change without affecting the registered output. Hence, “registered” can be thought of as “registration”, in this case, registration to the edge of a pulsed clock signal. The highest speed at which a synchronous digital circuit can be operated is limited by the frequency of the clock pulses, and this frequency is limited by the longest combinational circuit path. Careful management of the delay effects and knowing when new inputs can be provided to the circuitry and when the clock can be “advanced” are the hallmarks of the present art of high-performance digital design. The registers in clocked-mode circuitry clearly facilitate the stability necessary for achieving this performance. Furthermore, when registers can provide feedback to the combinational network, they permit history-dependent behavior. The registers that are fed back into the combinational circuitry block can be said to encode state information.
Since combinational circuitry generates output(s) based on a Boolean function of one or more (or all) inputs, they can generate the value of, among other things, the value of the next state. Decoupled by the synchronization structure provided through the register array, this state is latched in by the clock to become the “new” (next) state. Finite state machine (FSM) behavior is strictly a manifestation of the existence of state information, hence the use of feedback is necessary for implementing complex digital systems. Generation of both outputs and states is accomplished through the combinational circuitry, and the snapshot of the current, correct outputs and states is accomplished through the register array.
It is important to observe the two extremes under which the combinational part of the synchronous digital system can be implemented. In the first extreme case, a combinational circuit can be represented as a very large look-up table (LUT). Since a combinational circuit with m inputs can be completely specified by truth table of 2
m
entries, it is simple conceptually to consider a circuit where all of these entries are contained in an electronic LUT, which i

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