Multi-master multi-slave system bus in a field programmable...

Details Multi-master multi-slave system bus in a field programmable... Multi-master multi-slave system bus in a field programmable...

2001-05-25

2002-11-19

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S037000

Reexamination Certificate

active

06483342

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to field programmable gate arrays (FPGAs). In particular, it relates to the implementation of improved architectures and functions within an FPGA.
2. Background of Related Art
A Field Programmable Gate Array (FPGA) is a programmable integrated circuit which provides a customized logic array and functionality to a particular customer.
FIG. 4
depicts a conventional Field Programmable Gate Array (FPGA).
In particular, as shown in
FIG. 4
, an FPGA
400
typically includes four distinct features: configuration memory
406
, input/output (I/O) blocks
408
-
414
, configurable logic blocks
404
, and a routing network
402
between the internal components.
Configuration memory
406
provides access between the elements of the FPGA
400
and one external controlling device (e.g., a programmer). Based on the contents of the configuration memory
406
, various logical functions of the configurable logic blocks
404
are enabled and wired together via a configuration of the routing network
402
. Similarly, certain logic blocks are provided I/O access through various types of I/O devices
408
-
414
, as determined by both the configuration memory
406
and the routing provided by the routing network
402
.
The configuration memory
406
may be, e.g., static RAM (SRAM). The configuration memory bits turn elements or switches on or off in embedded elements of the configurable logic blocks
404
, and establish routing between elements of the FPGA
400
, to define the functionality of the FPGA
400
.
Typically, individual memory bits of the configuration memory
406
define the desired functionality of the FPGA device
400
. These configuration memory bits are conventionally loaded one at a time using data lines and address lines directly to the configuration memory
406
(e.g., SRAM) over an external bus
420
from an external source. All embedded elements are programmed similarly using the same format to the configuration memory
406
.
Other types of configuration memory
406
typically include, e.g., EPROM or EEPROM, anti-fused, fused, or other storage devices, providing either one-time programmability, or multiple reprogrammability. The configuration memory
406
may be formed of one or more types of memory (e.g., SRAM and EEPROM).
The I/O blocks
408
-
414
conventionally provide direct connection between an internal, embedded component of the FPGA
400
, and external devices. The I/O blocks
408
-
414
may be hard-wired and/or configured and routed based on the user-instructed configuration stored in the configuration memory
406
.
The configuration memory
406
is loaded, or programmed, before use of the FPGA
400
. Before the FPGA
400
is configured, no external devices other than the single programming device connected to the external access bus
420
are permitted to communicate with embedded elements of the FPGA
400
(e.g., with the configurable logic blocks
404
).
The routing network
402
is programmably defined by the configuration memory
406
to route signaling between the internal logic blocks of the FPGA. The routing network
402
carries signal traffic between the various internal, embedded components of the FPGA
400
. Some portions of the routing network
402
may be directly connected or hard wired and/or may not be fully programmable by the user.
FPGA devices often include embedded run-time memory
450
in addition to the configuration memory
406
. The embedded run-time memory
450
is accessible until configuration of the FPGA
400
is complete. Moreover, the configuration memory
406
is generally not reprogrammed while the FPGA device
400
is in operation.
FPGA devices
400
are typically programmed using an appropriate configuration and routing software application which inputs a user's particular requirements, and determines a best configuration of the
15
routing of the FPGA
400
by steps generally referred to as “partitioning”, “placing”, and “routing”, to ultimately configure the elements of the FPGA
400
to meet the particular user's needs.
FPSCs, a more recent derivation of an FPGA, combines field programmable logic with ASIC or mask programmed logic into a single device. FPSCs provide the quick time to market and flexibility inherent in FPGAs, the design effort savings inherent from the use of software driven cores, as well as the speed, design density, and economy inherent in application specific integrated circuits (ASICs).
Embedded cores within an FPSC can take many forms. Generally, the embedded cores available within an FPSC are selected from an ASIC library, but customer specific FPSCs may be developed to include one or more custom, proprietary or otherwise unique embedded core supplied by the user.
In conventional devices, pre-programming of application specific blocks (ASB blocks) and configuration memory was performed through configuration logic. However, conventional FPGA configuration logic is not available for access or use by FPGA components after configuration, leading to inefficient and slow implementations. Moreover, as shown in
FIG. 4
, the functionality of the FPGA
400
or FPSC is conventionally programmed by only one master device (e.g., a microprocessor) having direct access to the configuration memory
406
of the device, and reconfiguration during use if not permitted.
There is thus a need for a more flexible FPGA device, allowing efficient and faster implementations, and greater access.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a Field Programmable Gate Array comprises a plurality of master and/or slave elements, and an embedded system bus between the plurality of master and slave elements. An external interface provides external access to the embedded system bus from a device external to the Field Programmable Gate Array.
A method of providing external access to any one of a plurality of master and/or slave elements in a Field Programmable Gate Array in accordance with another aspect of the present invention comprises providing an embedded system bus between a plurality of master and/or slave elements. An external interface is provided on the system bus. The external interface provides access between the embedded system bus and a device external to the Field Programmable Gate Array. The external interface is another master element. All accesses are available on the system bus independent of the state of the FPGA configuration.


REFERENCES:
patent: 6034542 (2000-03-01), Ridgewy
patent: 6094065 (2000-07-01), Tavana et al.
patent: RE37195 (2001-05-01), Kean

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