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I/O buffer power up sequence

Electronic digital logic circuitry – Interface – Logic level shifting
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I2C repeater with voltage translation

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer circuit and method

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer circuit including an input level translator with sl

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer for multiple differential I/O standards

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer for multiple differential I/O standards

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer for multiple differential I/O standards

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer for translating TTL levels to CMOS levels

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer utilizing a cascode to provide a zero power TTL to

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer with stabilized trip points

Electronic digital logic circuitry – Interface – Logic level shifting
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Input buffer with voltage clamping for compatibility

Electronic digital logic circuitry – Interface – Logic level shifting
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Input circuit

Electronic digital logic circuitry – Interface – Logic level shifting
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Input circuit

Electronic digital logic circuitry – Interface – Logic level shifting
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Input circuit for level-shifting TTL or CMOS to ECL signals

Electronic digital logic circuitry – Interface – Logic level shifting
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Input circuit having current control

Electronic digital logic circuitry – Interface – Logic level shifting
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Input circuit receiving input signal of TTL level

Electronic digital logic circuitry – Interface – Logic level shifting
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Input/output device with fixed value during sleep mode or at...

Electronic digital logic circuitry – Interface – Logic level shifting
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Integrated buffer circuit

Electronic digital logic circuitry – Interface – Logic level shifting
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Integrated buffer circuits having improved noise immunity and TT

Electronic digital logic circuitry – Interface – Logic level shifting
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Integrated circuit device including CMOS tri-state drivers...

Electronic digital logic circuitry – Interface – Logic level shifting
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