Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-07-31
2003-05-20
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S063000, C326S080000, C326S081000
Reexamination Certificate
active
06566909
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit device including a circuit for powering down by halting power supply.
2. Description of Related Art
Power saving of integrated circuit devices increases importance with the widespread of equipment such as mobile telephones, which supplies power to integrated circuits from a battery. To save consumption current of the integrated circuits, power supply to semiconductor devices can be suspended in accordance with the operating state of the equipment.
FIG. 6
shows a CMOS tri-state driver embedded in a conventional integrated circuit, and
FIG. 7
shows an example of an output circuit using the CMOS tri-state driver of FIG.
6
. In
FIG. 6
, the CMOS tri-state driver
120
consists of a P-channel MOS transistor
121
and an N-channel MOS transistor
122
which are connected in series. In
FIG. 7
, the output circuit produces an output signal Q that assumes one of the three logical levels “H” (high), “L” (low) and “Z” (high-impedance) in response to a drive control signal EN and an output data signal D. The power supply to all the logic gates is denoted by VDD.
FIG. 8
is a truth table of the output circuit of FIG.
7
.
FIG. 9
shows a CMOS level converter for converting the voltage amplitude of an internal signal of a conventional integrated circuit. It is used for converting the voltage amplitude when the voltage amplitude of an input/output signal of the integrated circuit is greater than that of its internal signal. Using internal signals of a reduced voltage amplitude in the integrated circuit is effective to save its power. As a relevant prior art, a “Strong ARM processor” is known which is disclosed on page 121 of “HOT Chips 8-1996 Symposium Record”.
In
FIG. 9
, DH and DL designate complementary inputs, and QH and QL designate complementary outputs. The “H” voltage of the input signals DH and DL is lower than the voltage supplied to P-channel MOS transistors P
1
and P
2
of the level converter. Circuit constants of the P-channel MOS transistor P
1
and N-channel MOS transistor N
1
are set in advance such that when the N-channel MOS transistor N
1
is brought into conduction, the potential of the output signal QL is sufficiently dropped to such a level that brings the P-channel MOS transistor P
2
into conduction.
Likewise, circuit constants of the P-channel MOS transistor P
2
and N-channel MOS transistor N
2
are set in advance such that when the N-channel MOS transistor N
2
is brought into conduction, the potential of the output signal QH is sufficiently dropped to such a level that brings the P-channel MOS transistor P
1
into conduction.
When the input signals DH and DL are placed at “H” and “L”, respectively, the N-channel MOS transistor N
1
is brought into conduction and the N-channel MOS transistor N
2
is brought out of conduction. This drops the potential of the output signal QL, and brings the P-channel MOS transistor P
2
into conduction, thereby raising the potential of the output signal QH, and bringing the P-channel MOS transistor P
1
out of conduction. Thus, the output signal QH becomes “H”, and the output signal QL becomes “L”. In this case, the potential difference between the output signals QH and QL equals the potential difference between the source terminals of the P-channel MOS transistors and N-channel MOS transistors of the level converter. Thus, the output signals QH and QL can be obtained with a potential difference varying from that between the input signals DH and DL.
FIG. 10
is an example of a conventional output circuit combining the CMOS tri-state driver of
FIG. 6
with the CMOS level converter of FIG.
9
. The output circuit operates just as that of
FIG. 7
except that the voltage amplitude of the drive control signal EN and output data signal D differs from that of the output signal Q. The power to all the logic gates is supplied from an internal power supply with a voltage lower than VDD.
FIG. 11
shows an input/output circuit using the output circuit of FIG.
7
. As is well known, a plurality of such input/output circuits are usually connected together to each line of a bus, and are controlled such that only one of them drives the line of the bus at a time. The input/output circuit includes the CMOS tri-state driver
120
consisting of the P-channel MOS transistor
121
and the N-channel MOS transistor
122
which are connected in series; and a controller circuit for controlling the CMOS tri-state driver
120
. The input/output circuit places, when the drive control signal EN is “L”, its output signal Q at the high-impedance state “Z” regardless of the level of the output data signal D so that another input/output circuit connected to the same line can drive its output signal Q to “H” or “L”. In addition, the input/output circuit transfers the level changes of the output signal Q as an input data signal N. The power supply to all the logic gates in the output/input circuit is VDD.
FIG. 12
shows an input/output circuit employing the output circuit as shown in FIG.
9
. The input/output circuit operates just as that of
FIG. 11
except that the voltage amplitude of the drive control signal EN and output data signal D differs from that of the output signal Q. The power to all the logic gates is supplied from an internal power supply with a voltage lower than VDD.
FIG. 13
shows an example of a computer system configured by applying integrated circuits including the input/output circuits of FIG.
11
. In
FIG. 13
, a CPU and a system control LSI share a memory and bus A, and employ the input/output circuits as shown in FIG.
11
. When the data transfer between the CPU and memory is enabled by a control signal B from the system control LSI to the CPU, the output circuits of the system control LSI place the bus A at high-impedance state “Z” so that the CPU carries out the data transfer with the memory through the bus A. In contrast, when the data transfer between the CPU and memory is disabled by the control signal B from the system control LSI to the CPU, the output circuits of the CPU place the bus A at the high-impedance state “Z” so that the system control LSI carries out the data transfer with the memory through the bus A.
In the computer system as shown in
FIG. 13
, the consumption power can be greatly reduced by shutting off the power supply to the CPU, when only the system control LSI and memory must be operated. The conventional computer system, however, has a problem of not being able to achieve sufficient power saving because of a drawback involved in the conventional CMOS tri-state drivers employed by the CPU. This will be described in more detail with reference to
FIG. 14
illustrating the P-channel MOS transistor
121
of
FIGS. 11 and 12
which has its source and backgate connected together to the power supply VDD and its drain connected to a line of the bus. Shutting off the power supply of the CPU (for powering down) will drop the potential of the source, backgate and drain of the P-channel MOS transistor
121
of the CMOS tri-state driver
120
. If the system control LSI supplies the bus A with a signal of logic “H” in this case, a forward current will flow through the PN junction between the drain and the backgate of the P-channel MOS transistor
121
of the CMOS tri-state driver
120
as shown in FIG.
14
. This is because the power supply to CPU is interrupted during the powerdown, and hence the source, which is connected to the power supply of the CPU, is placed at logic “L”. Thus, electric charges are supplied from the output terminal of the system control LSI to the power supply terminal of the CPU, thereby hindering the power saving.
In view of this, a CMOS tri-state driver disclosed in Japanese patent application laid-open No. 8-307238/1996, for example, has an additional circuit for supplying the P-channel MOS transistor with a backgate potential as shown in
FIG. 15
to prevent the leakage current from flowing into the CPU even during the power shutdown. Although it can prevent the forward current t
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Tokar Michael
Tran Anh Q.
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