Integrated buffer circuit

Details Integrated buffer circuit Integrated buffer circuit

1998-10-19

2000-05-30

Santamauro, Jon

Electronic digital logic circuitry

Interface

Logic level shifting

326 81, 326 83, H03K 190185

Patent

active

060694912

ABSTRACT:
The buffer circuit of the invention converts TTL level input signals to CMOS level output signals. The buffer circuit has three inverter stages, in which the output signal of one stage is positively fed back, in order to achieve complete modulation. Because of a current limiting circuit, the current consumption of the buffer circuit does not exceed a defined value. Despite a high switching speed, the power consumption of the circuit is low.

REFERENCES:
patent: 4501978 (1985-02-01), Gentile et al.
patent: 4700086 (1987-10-01), Ling et al.
patent: 4713561 (1987-12-01), Yamada
patent: 5117131 (1992-05-01), Ochi et al.
patent: 5144167 (1992-09-01), McClintock
patent: 5349246 (1994-09-01), McClure
patent: 5412331 (1995-05-01), Jun et al.
patent: 5565795 (1996-10-01), Kawano
patent: 5831452 (1998-11-01), Nowak et al.
Japanese Patent Abstract No. 60-70822 (Sasaki et al.), dated Apr. 22, 1985.
Japanese Patent Abstract No. 61-62230 (Takeuchi), dated Mar. 31, 1986.

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