Integrated buffer circuits having improved noise immunity and TT

Details Integrated buffer circuits having improved noise immunity and TT Integrated buffer circuits having improved noise immunity and TT

1998-09-08

2000-08-01

Tokar, Michael

Electronic digital logic circuitry

Interface

Logic level shifting

326 65, 326 70, 326 76, 326 83, 326 85, 326 86, 326 87, H03K 19175

Patent

active

060972165

ABSTRACT:
Integrated buffer circuits which are less susceptible to noise and provide TTL-to-CMOS signal conversion capability include a first TTL-compatible inversion buffer, a second CMOS-compatible inversion buffer having an input electrically coupled to an output of the first inversion buffer and a preferred pull-up (or pull-down) circuit to improve noise immunity. The preferred circuit pulls the output of the first inversion buffer to a potential of the first reference signal line (e.g., Vdd) in response to a signal at an output of the second inversion buffer and a signal at an input of the first inversion buffer. This circuit comprises a first field effect transistor having a gate electrode electrically coupled to the output of the second inversion buffer and a second field effect transistor having a gate electrode electrically coupled to the input of the first inversion buffer. These first and second field effect transistors are electrically coupled in series so that a first source/drain of the first field effect transistor is electrically connected to a first source/drain of the second field effect transistor. In addition, a second source/drain of the first field effect transistor may be electrically connected to the first reference signal line and a second source/drain of the second field effect transistor may be electrically connected to the output of the first inversion buffer.

REFERENCES:
patent: 4612461 (1986-09-01), Sood
patent: 5223751 (1993-06-01), Simmons et al.
patent: 5304867 (1994-04-01), Morris
patent: 5892372 (1999-04-01), Ciraula et al.

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