Input buffer for multiple differential I/O standards

Details Input buffer for multiple differential I/O standards Input buffer for multiple differential I/O standards

2007-05-08

2007-05-08

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S083000, C327S408000

Reexamination Certificate

active

11000472

ABSTRACT:
An input buffer circuit has a plurality of selectively enabled differential amplifier circuits, where each differential amplifier is configured for compatibility with a particular differential I/O standard and its corresponding input operating range. For example, the input buffer may have two differential amplifiers suitable for receiving LVDS differential input signals over a wide input operating range, and another differential amplifier suitable for receiving the PCML differential input signals. One or more control signals are provided to the input buffer, e.g., programmably, to selectively enable the required differential amplifier(s) for a given I/O standard.

REFERENCES:
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patent: 5604460 (1997-02-01), Sehrig et al.
patent: 6023175 (2000-02-01), Nunomiya et al.
patent: 6137306 (2000-10-01), Hirata et al.
patent: 6218858 (2001-04-01), Menon et al.
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 0818734 (1998-01-01), None

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