Input buffer for translating TTL levels to CMOS levels

Electronic digital logic circuitry – Interface – Logic level shifting

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Details

326 83, 327316, H03K 190185, H03K 190948

Patent

active

054867789

ABSTRACT:
An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ended bias voltage (e.g. 3 V) related to the second terminal voltage. The bias voltage is servoed to regulate the second terminal voltage (e.g. 1.5 V) and the bias voltage (e.g. 3 V) regardless of energizing voltage variations. In response to the bias voltage and a variable input voltage, a pass transistor in a buffer produces a first control voltage different from the bias voltage by the pass transistor threshold voltage for input voltages greater than a value equal to the bias voltage less the pass transistor threshold, and corresponding to the input voltage for input voltages less than the bias voltage less the pass transistor threshold. The first control voltage is inverted to produce a second control voltage having the amplitude of the first control voltage for small amplitude values of the first control voltage, and having transition times and amplitudes of the first control voltage for large amplitude values of the first control voltage. A circuit differentially responds to the control voltage to produce an output voltage which rises and falls in accordance with the variations in the input voltage. The output voltage is servoed to limit the rises and falls.

REFERENCES:
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 4843264 (1989-06-01), Galbraith
patent: 5027008 (1991-06-01), Runaldue
patent: 5111080 (1992-05-01), Mizukami et al.
patent: 5113097 (1992-05-01), Lee
patent: 5204557 (1993-04-01), Nguyen

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