Input buffer circuit and method

Details Input buffer circuit and method Input buffer circuit and method

1996-06-04

1998-05-12

Santamauro, Jon

Electronic digital logic circuitry

Interface

Logic level shifting

326 34, 326 83, H03K 190185, H03K 190948

Patent

active

057511667

ABSTRACT:
A method and a circuit for automatically adjusting a switching threshold of an input buffer circuit (100) to conform to an input signal V.sub.IN which can be from either a TTL or a CMOS logic family. A latch circuit (120) is initialized to set the switching threshold to that of one of the logic families. A level shifting circuit (130) has a switchable load which varies the switching threshold under the control of the latch circuit (120). The amplitude of the input signal V.sub.IN is detected in a threshold detector circuit (110). If the input signal V.sub.IN is a signal from the CMOS logic family, the latch circuit (120) changes state, switching the switchable load of the level shifting circuit (130) to adjust the switching threshold of the input buffer circuit (100).

REFERENCES:
patent: 4472647 (1984-09-01), Allgood et al.
patent: 4820937 (1989-04-01), Hsieh
patent: 4999529 (1991-03-01), Morgan, Jr. et al.
patent: 5304872 (1994-04-01), Avraham et al.

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