Input buffer with voltage clamping for compatibility

Details Input buffer with voltage clamping for compatibility Input buffer with voltage clamping for compatibility

2002-05-16

2004-03-30

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S037000, C326S062000, C326S063000

Reexamination Certificate

active

06714048

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an input/output buffer design capable of handling multiple types of signals. More particularly, the present invention relates to an input/output buffer capable of handling combinations of signals from different types of circuitry, such as Peripheral Component Interconnect (PCI) circuitry, Gunnings Transceiver Logic (GTL), Emitter Coupled Logic (ECL), Series Stub Terminated Logic (SSTL), or Pseudo Emitter Coupled Logic (PECL).
BACKGROUND
Circuits constructed in accordance with standards such as PCI, GTL, ECL, SSTL or PECL each have different high and low state characteristics. Although some of the states for different circuit types will have similar voltage and current requirements, others will be different.
PCI provides a high speed bus interface for PC peripheral I/O and memory and its input and output voltage and current requirements are similar to CMOS. For instance, the high and low voltage states will vary from rail to rail (VDD to VSS), with high impedance low current inputs and outputs.
GTL provides a lower impedance higher current high state, providing a low capacitance output to provide higher speed operation. The transition region for GTL is significantly smaller than for CMOS.
PECL provides a high current low voltage to provide a smaller transition region compared to CMOS to better simulate emitter coupled logic (ECL). The PECL offers a low impedance outputs and a high impedance inputs to be the most suitable choice of logic to drive transmission lines to minimize reflections.
Integrated circuit chips, such as a field programmable gate array (FPGA) chip, or a complex programmable logic device (CPLD), provide functions which may be used in a circuit with components operating with any of the logic types, such as PCI, GTL, ECL, PECL, or SSTL described above. It would be desirable to have an input/output buffer for use on a general applicability chip such as a FPGA or CPLD to selectively make the chip compatible with any of these logic types.
SUMMARY
In accordance with the present invention, an input/output buffer circuit includes an input buffer which can selectively be made compatible with any of a number of logic types, such as PCI, GTL, or PECL.
In accordance with the present invention, the input buffer portion of the input/output includes:
a first mode select input;
a second mode select input;
a buffer input;
a buffer output;
a first voltage clamp connected to the first mode select input, the buffer input, and the buffer output, the first voltage clamp limiting the buffer output voltage and current depending on the state of a signal received at the first mode select input when a signal is received at the buffer input in a first state; and
a second voltage clamp connected to the second mode select input, the buffer input, and the buffer output, the second voltage clamp limiting the buffer output voltage and current depending on a signal received at the first mode select input when a signal is received at the buffer input in a second state.
Limits on the voltage and current set depending on the first and second mode select inputs enable current and voltage from the input buffer to be compatible with GTL, PCI, PECL and other types of circuitry.


REFERENCES:
patent: 6005414 (1999-12-01), Reay
patent: 6028758 (2000-02-01), Sharpe-Geisler
patent: 6031365 (2000-02-01), Sharpe-Geisler
patent: 6218858 (2001-04-01), Menon et al.
U.S. patent application Ser. No. 10/146,826, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/146,769, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/147,199, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/146,734, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/147,011, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/151,753, Sharpe-Geisler, filed May 16, 2002.

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