Electronic digital logic circuitry – Interface – Logic level shifting
Patent
1997-08-04
2000-03-28
Santamauro, Jon
Electronic digital logic circuitry
Interface
Logic level shifting
326 80, 326 84, H03K 190175
Patent
active
060436786
ABSTRACT:
According to the present invention, an input circuit is provided comprising: an input terminal; a first power source terminal; a second power source terminal; a first bipolar transistor; a second bipolar transistor; a first electric current cut off member; a second electric current cut off member; a voltage clamping member; and a buffer. As a result, even when an electric potential greater than that of the power source voltage is applied to the input terminal, regardless of the supply or interruption of the power source voltage, destruction of the internal components is prevented and a steady-state electric current of the power source voltage and/or the input terminal is cut off. Hence, providing a PMOS transistor and NMOS transistor, serves to cut off the electric current routes of power source terminal VDD and the ground terminal. It is thus possible to cut off the electric current flowing from the power source terminal to the input and ground terminals while also preventing the destruction of the components relating to the increased signal.
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Patent Abstracts of Japan, vol. 010, No. 209 (E-421), Jul. 22, 1986 & JP 61 050421 A (Toshiba Corp; Others: 01), Mar. 12, 1986, * Abstract *.
Patent Abstracts of Japan, vol. 018, No. 161 (E-1526), Mar. 17, 1994 & JP 05 335930 A (Fujitsu Ltd; Others: 01), Dec. 17, 1993, * Abstract *.
NEC Corporation
Santamauro Jon
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