Logical operation circuit and logical operation method

Logical operation circuit employing two-terminal chalcogenide sw

Look-up table using multi-level decode

Low dissipation inverter circuit

Low jitter high speed CMOS to CML clock converter

Low jitter high speed CMOS to CML clock converter

Low leakage power programmable multiplexers

Low power clock buffer having a reduced, clocked, pull-down tran

Low power consuming logic circuit

Low power consumption and high speed NOR gate integrated circuit

Low power differential conductance-based logic gate and...

Low power multiplexer circuit

Low power multiplexer with shared, clocked transistor

Low power output buffer circuit

Low power wired OR

Low power wordline decoder circuit with minimized hold time

Low voltage bipolar logic and gate device

Low voltage bipolar transistor logic circuit

Low voltage differential logic

Low voltage high-speed differential logic devices and method...