Low voltage differential logic

Details Low voltage differential logic Low voltage differential logic

1999-12-10

2002-04-16

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S083000, C327S055000, C327S067000

Reexamination Certificate

active

06373292

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-speed electronic circuits. More particularly, the present invention provides a low-power, high speed VLSI apparatus using voltage scaling.
2. The Background Art
Increasing demands for smaller, better, and faster electronic circuits having increasingly greater levels of functionality in a smaller package have caused the power consumption of those circuits to become an increasingly critical factor in circuit design.
In most integrated circuits, it is considered beneficial to minimize the power consumption of individual circuits making up a system. Prior art VLSI systems use charge recycling differential logic (CRDL) circuits to transmit information from one location in an integrated circuit to another. One example of such a CRDL circuit is shown in FIG.
1
.
Referring to
FIG. 1
, CRDL circuit
10
includes transistors
12
,
14
,
16
,
18
,
20
,
22
,
24
,
26
and
28
. As with other dynamic circuits, circuit
10
operates in two phases, a precharge phase, and an evaluation phase. In the precharge phase, clock line
30
is high, connecting output nodes
32
and
34
together through NMOS transistor
28
. The precharge voltage at the pull-up node is roughly half the supply voltage.
In the evaluation phase, the clock signal is low, turning transistor
28
off which breaks the connection between the gates of transistors
12
and
14
. As the voltage level of one of the precharged output nodes
32
or
34
begins to go low, the other node is pulled high by the cross-coupled pair of PMOS transistors. An enable signal going high at this time on enable line
36
turns on transistor
24
accelerating the pull-down. At the same time, one of transistors
16
or
22
turns on enable output
38
so the next stage circuit may be enabled.
While prior art circuits such as that seen in
FIG. 1
are useful for their intended purpose, the supply voltages required to operate the circuit are higher than necessary and therefore cause unnecessary power consumption. The supply voltages required for the circuits just described are four to five times the threshold voltage of the transistors employed in the design. Therefore, it would be beneficial to provide circuitry which performs the same function while consuming much less power by lowering the required supply voltage to a value less than four times the threshold voltage.
SUMMARY OF THE INVENTION
A low voltage differential circuit is described herein including a complementary logic tree having first, second and third inputs and two outputs, the logic tree for performing a desired logical function on signals received at the first input, thereby opening a pathway for current flow between at least one of the following: the second input and the first output, the second input and the second output, the third input and the first output, the third input and the second output. The circuit further includes a first transistor having a first gate, a first source, and a first drain, the first drain connected to the first output, the first source being connected to a supply voltage, a second transistor having a second gate, a second source, and a second drain, the second source connected to the first gate, the second drain connected to the first drain; and a third transistor having a third gate, a third source, and a third drain, the third source being connected to a supply voltage, the third gate being connected to the second drain, the third drain connected to the second source and the second output.


REFERENCES:
patent: 5859548 (1999-01-01), Kong
patent: 6016065 (2000-01-01), Kong
Bai-Sun Kong et al., “Charge Recycling Differential Logic for Low-Power Application,” IEEE International Solid-State Conference, Feb. 1996.
Swee Yew Choe et al., “Half-Rail Differential Logic,” IEEE International Solid-State Circuits Conference, Feb. 1997.
Swee Yew Choe et al., “Dynamic Half Rail Differential Logic for Low Power,” Jun. 1997.

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