Low power multiplexer with shared, clocked transistor

Details Low power multiplexer with shared, clocked transistor Low power multiplexer with shared, clocked transistor

1999-06-30

2000-08-29

Nguyen, Tan T.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

121105, 121106, H03K 1920

Patent

active

061114359

ABSTRACT:
A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

REFERENCES:
patent: 5592107 (1997-01-01), McDermott et al.
patent: 5889416 (1999-03-01), Lovett
patent: 5986480 (1999-11-01), Sharpe-Geisler

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