Low leakage power programmable multiplexers

Details Low leakage power programmable multiplexers Low leakage power programmable multiplexers

2007-11-20

2007-11-20

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S041000

Reexamination Certificate

active

11158579

ABSTRACT:
An integrated circuit programmable multiplexer that reduces sub-threshold leakage current in deep sub-micron technology. The multiplexer uses a plurality of transistor stages, wherein each transistor of a subsequent stage is connected to at least two transistors of a prior stage, such that each transistor is in series with at least one other transistor. Transistors that are not part of the signal path through the multiplexer are deactivated, wherein a series of two or more deactivated transistors have significantly less sub-threshold leakage current than a single deactivated transistor. Configuration memory cells that store and communicate control signals to the multiplexer transistors are also connected to a low-voltage power supply when the multiplexer is not in use to reduce leakage current through the memory cells.

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Rahman, Arifur et al.; “Evaluation of Low-Leakage Design Techniques for Field Programmable Gate Arrays,” FPGA 2004, Feb. 22, 2004, pp. 23-29, Available from Department of Electrical and Computer Engineering, Polytechnic University, Brookly, NY 11201.
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K. Roy et al., “Leakage Current Mechanisms and Leakage Reduction Techniques in Deep- Submicrometer CMOS Circuits,” Proceedings of the IEEE, vol. 91 (2), pp. 305-327. Feb. 2003.

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