Low power wordline decoder circuit with minimized hold time

Details Low power wordline decoder circuit with minimized hold time Low power wordline decoder circuit with minimized hold time

1999-02-16

2001-01-09

Santamauro, Jon (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S098000, C326S121000

Reexamination Certificate

active

06172531

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to clocked decoder circuits, and more particularly to, an improved wordline decoder circuit.
DESCRIPTION OF THE RELATED ART
Clocked NOR decoders are common in the art. For example, U.S. Pat. No. 5,737,270 discloses NOR decoders with locally generated clocks.
FIG. 1
shows a precharged wordline decoder disclosed by U.S. Pat. No. 5,737,270. Precharged wordline decoder includes a first NOR decoder formed of multiple N-channel field effect transistors NFETs N
0
, N
1
, and NN connected between word OR top node (WORT) and word OR bottom node (WORB), respectively receiving address bits A
0
-AN. Precharged wordline decoder includes precharge P-channel field effect transistors PFETs P
1
and P
2
, respectively precharging WORT and WORB nodes, and a discharge N-channel field effect transistor NFETs ND
1
. In the NOR decoder, a first local clock CLKA is applied to discharge NFET ND
1
and to a clock delay circuit formed by inverters INV
1
, INV
2
. The clock delay circuit generates a locally-controlled delayed clock signal CLXB. A driver logic NAND circuit is formed by a driver NFET NDR, a precharge PFET P
3
, a discharge NFET ND
2
, clamping PFETs P
4
and P
5
, and an inverter INV
3
.
In
FIG. 1
, driver logic NAND circuit receives the locally-controlled delayed clock signal CLKB that is applied to the gates of precharge PFET P
3
and discharge NFET ND
2
. The gates of precharge PFETs P
1
and P
2
are connected to the gates of precharge PFET P
3
and discharge NFET ND
2
receiving delayed clock signal CLKB. The delayed clock signal CLKB disables the precharge PFETS P
1
and P
2
of the first NOR decoder. The gate of NFET NDR is driven by the output of NFETs N
0
, N
1
, through NN. The drain of driver NFET NDR at node labeled WLB is connected to the input of inverter INV
3
which provides the wordline output indicated at line WORDLINE. The clamping PFETs P
4
and P
5
respectively hold a high voltage level at nodes WLB and WORDLINE, preventing the decoder circuit from misdecoding due to a drop in the voltage level at the output nodes of the clamping devices. The driver logic NAND circuit receives the delayed clock signal CLKB for controlling the wordline driver devices, NFET NDR and inverter INV
3
.
Many existing decoder circuits have significant power requirements. Often required long hold times of existing decoder circuits are accommodated by delaying the data, thus adding area and impacting other aspects of performance.
Many existing decoder circuits have gating signals other than address bits, such as thread-select or enable to determine when the decoded signal is to be activated. In the common implementation of the clocked NOR decoder, an additional NOR device can be added. However an additional input will increase the NOR node loading and reduce performance slightly. In the case of a thread-select signal, the penalty is much greater. The thread-select function indicates the address decoding for the A-thread, is unique from the B-thread. Normally, the decodes would have to be duplicated using two copies of the illustrated decoder of FIG.
1
. One copy is active when the A-thread is selected, and the other being active when the B-thread is selected. The loading penalty on the address inputs is doubled by the addition of the thread-select function. In many designs, this additional loading is not tolerable due to the additional setup time it puts on the address inputs.
While the NOR decoder circuits of U.S. Pat. No. 5,737,270 provides improved performance over many existing decoder circuits, a need exists for an improved clocked NOR decoder circuit having improved power dissipation. It is desirable to provide improved hold time of NOR decoders with local clocks. It is desirable to provide an improved precharged wordline decoder with improved input loading characteristics.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an improved wordline decoder circuit. Other objects are to provide such improved wordline decoder circuit enabling improved power dissipation; to provide such improved wordline decoder circuit enabling improved hold time performance and to provide such improved wordline decoder circuit substantially without negative effects and that overcomes many of the disadvantages of prior art arrangements.
In brief, a wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.


REFERENCES:
patent: 4692637 (1987-09-01), Shoji
patent: 5291076 (1994-03-01), Bridges et al.
patent: 5737270 (1998-04-01), Oppold et al.
patent: 5757205 (1998-05-01), Ciraula et al.
patent: 5825208 (1998-10-01), Levy et al.
patent: 5841304 (1998-11-01), Tam
patent: 5917355 (1999-06-01), Klass

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