Low power output buffer circuit

Details Low power output buffer circuit Low power output buffer circuit

1995-11-13

1997-08-12

Westin, Edward

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 17, 326 68, 326 83, H03K 1900

Patent

active

056569556

ABSTRACT:
A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

REFERENCES:
patent: 4978870 (1990-12-01), Chen et al.
patent: 5216295 (1993-06-01), Hoang
patent: 5486777 (1996-01-01), Nguyen
Flynn, et al: "A 1.2-um CMOS Current-Controlled Oscillator"; pp. 982-987, Jul. 1992; IEEE Journal of Solid-State Circuits, vol. 27, No. 7.
Chao, et al.: "A 140 Mbit/s CMOS LSI Framer Chip for a Broad-Band ISDN Local Access System"; Feb. 1988, pp. 133-141; IEEE Journal of Solid-State Circuit, vol. 23, No. 1.
Young, et al: "A PLL Clock Generator with 5 to 110 MHz of Lock Range of Microprocessors"; Nov. 1992, pp. 1599-1606; IEEE Journal of Solid-State Circuits, vol. 27, No. 11.

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