Low power clock buffer having a reduced, clocked, pull-down tran

Details Low power clock buffer having a reduced, clocked, pull-down tran Low power clock buffer having a reduced, clocked, pull-down tran

1999-06-30

2000-09-26

Nguyen, Tan T.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326119, H03K 190948

Patent

active

061247375

ABSTRACT:
A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.

REFERENCES:
patent: 5831453 (1998-11-01), Stamoulis et al.
patent: 5892372 (1999-04-01), Ciraula et al.

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