Look-up table using multi-level decode

Details Look-up table using multi-level decode Look-up table using multi-level decode

1999-09-23

2002-02-26

Lam, Tuan T. (Department: 2816)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C327S408000

Reexamination Certificate

active

06351152

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to electronic look-up table circuits and specifically to a look-up table circuit that uses combinational logic to generate internal enable signals in a programmable logic array application.
BACKGROUND OF THE INVENTION
Look-up table circuits are well known in the art for selecting one of several signal inputs and passing the selected signal input to the output of the circuit. Look-up tables are widely used in applications such as communications, digital computing, control systems, etc.
FIG. 1
shows a block diagram of a look-up table
100
having signal inputs
102
, select lines
104
and output
106
. In operation, signal inputs
102
are applied with electrical signals in the form of, e.g., digital data, represented by high and low voltages corresponding, respectively, to 1′s and 0's. Select lines
104
are similarly applied with high or low signals. The specific pattern of high or low signals at select lines
104
determines which of signal inputs
102
is connected to output
106
. Once the connection is made between a signal input and the output, or, equivalently, a signal is selected and “passed” to the output, the passed signal is then available at the output after a short delay. Signal inputs are, typically, outputs from a memory element such as random access memory (RAM) or read-only memory (ROM).
As an example, assume that only select lines
108
and
112
are used. Further, assume that there are only four signal inputs
102
. A common operation of the look-up table is then as follows: When select line
108
and select line
112
are both low, input
114
is passed to output
106
. When select line
108
is low and select line
112
is high, input
116
is passed to output
106
. When select line
108
is high and select line
112
is low, input
118
is passed to output
106
. Finally, when select line
108
and select line
112
are both high, signal input
120
is passed to output
106
. Thus, by using a binary numbering scheme at the select lines
104
, signal inputs are passed to the output according to their number corresponding with their position from top to bottom in FIG.
1
.
FIG. 2
is a schematic diagram of a prior art look-up table circuit. In
FIG. 2
, look-up table circuit
150
includes select lines A, B, C and D at
152
, signal inputs R0-15 at
154
and outputs, LOUT, at
156
.
In the circuit of
FIG. 2
, voltages in the form of digital signals are applied to signal inputs
154
and select lines
152
. For example, in a typical implementation, the voltages may correspond to 0 volts for a “low” and 5 volts for a “high.” With a low voltage corresponding to a “0” binary digit and a high voltage corresponding to a “1” binary digit there are 16 possible combinations of voltages that can be applied to select lines
152
to select one of the 16 signal inputs
154
as shown in Table I below.
TABLE I
DCBA
LOUT
1111
R0
1110
R1
1101
R2
1100
R3
1011
R4
1010
R5
1001
R6
1000
R7
0111
R8
0110
R9
0101
  R10
0100
  R11
0011
  R12
0010
  R13
0001
  R14
0000
  R15
As shown in Table I, where select lines A, B, C and D are each supplied with a high voltage, the signal input R
0
is the signal seen at the output
156
, LOUT. This can be verified by tracing signal input R
0
to transistor
158
. Since select line A is high, transistor
158
will be on and signal input R
0
will be passed to transistor
160
. Since select line B is high, signal input R
0
will further be passed to transistor
162
. Likewise, select lines C and D are high so that transistors
162
,
164
will pass signal input R
0
to LOUT at
156
.
The transistors are grouped into four stages corresponding to the order in which a signal passes through the transistors. First stage
176
includes transistor
158
, second stage
178
includes transistor
160
, third stage
180
includes transistor
162
and fourth stage
182
includes transistor
164
.
In the circuit of
FIG. 2
, each of the transistors
152
,
160
,
162
and
164
that passes signal input R0 to LOUT introduces a delay referred to as a “transistor delay.” In a typical metal-oxide-semiconductor (“MOS”) implementation, a single transistor delay is about 0.3 nS. Thus, the total propagation delay through the circuit of
FIG. 2
is 1.2 nS.
A second example to illustrate the performance of the look-up table circuit of
FIG. 2
assumes that the select lines have the value “1110” so that select lines D, C and B are high while select line A is low. This means that signal input R
1
will be passed to LOUT. However, in order for signal input R
1
to be passed to LOUT, transistor
174
must be on. Since select line A is low at the input to inverter
172
the gate of transistor
174
will be high so that transistor
174
is on.
An MOS inverter such as inverter
166
,
168
,
170
or
172
each has an inverter delay or about 0.5 Ns. In the cases where an inverted select line signal is used to pass a signal input, the delay of the inverter must be taken into account. Thus, where signal input R
1
is passed through transistor
174
by enabling the gate of transistor
174
with the output of inverter
172
, the delay in the first stage is the time required to turn transistor
174
on (0.5 nS) plus the transistor delay time in passing the signal from the source to the drain (0.3 nS). This gives a total time through a first stage transistor with an inverted select line signal at its gate of 0.8 nS.
The inverter delay of 0.5 nS is not a factor in later stages
2
,
3
or
4
since after the first 0.5 nS of operation of the circuit the output of each inverter is available. This is because the select line signals propagate through the inverters “concurrently” or “in parallel.” Thus, later stages only introduce a single transistor delay of 0.3 Ns. This means that the worst case total delay in passing a signal input to the output is about 1.7 nS. The general “best case” delay, for purposes of this discussion, is about 1.2 nS which occurs when a signal is passed through transistors that do not have an inverted select line controlling the transistor gate in the first stage. (A “special best case” delay not considered in this discussion occurs when select line D goes from low to high while select lines A, B and C do not change. This introduces only a 0.3 nS delay through transistor
164
before the signal at output
156
is valid.)
Thus, it is seen in the prior art circuit of
FIG. 2
that the delay in selecting a signal and making the signal available at the output, LOUT, is in the range of 1.2 nS to 1.7 nS. Naturally, it is desirable to reduce this delay as much as possible.
SUMMARY OF THE INVENTION
The present invention is a look-up table circuit that provides for a reduced lay time in selecting and passing a signal input to the output. The invention includes combinational means such as NOR gates to derive signals based on two or more select lines. The output of the combinational means is used to enable transistors to pass the selected signal to the output.
A preferred embodiment implements a 16 input look-up table by having two of the four select lines used to derive inputs to four NOR gates. The resulting circuit requires only three transistor stages and thus reduces the delay time over prior art circuits such as the circuit of FIG.
2
.


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