LandOfFree - US Patents - Listing for Electrical computers and digital processing systems: support,Synchronization of clock or timing signals, data, or pulses,Using delay

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Method of timing calibration using slower data rate pattern

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Method of timing calibration using slower data rate pattern

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Method of timing calibration using slower data rate pattern

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Methods and systems to reduce data skew in FIFOs

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

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Methods for generating a delayed clock signal

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

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Methods of determining whether a network interface card...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multi-bit deskewing of bus signals using a training pattern

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

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Multi-component module fly-by output alignment arrangement...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multi-link extensions and bundle skew management

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

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Multi-link receiver and method for processing multiple data...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multi-link receiver and method for processing multiple data...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multi-link receiver mechanism for processing multiple data...

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multi-mode buffer for digital signal processor

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Patent

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Multi-output monolithic device without generating simultaneous s

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Patent

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Multiprotocol computer bus interface adapter and method

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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Multistage clock delay circuit and method

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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