Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Patent
1998-08-18
2000-12-05
De Cady, Albert
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
710 65, 710 58, G06F 1100
Patent
active
061580139
ABSTRACT:
The invention relates to a multi-output monolithic device, and particularly to a multi-output monolithic integrated circuit device without generating a simultaneous switch output (SSO) in communication or in a network, in which the plurality of output port will not switch from "0" to "1" or from "1" to "0" simultaneously to prevent insufficient power supply caused by a simultaneous switch, resulting in noise generation and errorous operations. A multi-bit shift register in used in the invention to make each output port have a different and to reduce the probability of the same output value on each output port, thereby reducing the influence of SSO. Then, a slightly different delay is made of each output port during output, so as to eliminate SSO.
REFERENCES:
patent: 4409592 (1983-10-01), Hunt
patent: 4890009 (1989-12-01), Miyazaki et al.
patent: 4910735 (1990-03-01), Yamashita
patent: 5727212 (1998-03-01), Dinallo
patent: 5929683 (1999-07-01), Menkhoff
patent: 5944833 (1999-08-01), Ugon
patent: 5948102 (1999-09-01), Wuidart
Chow Yu-Chun
Lee Chun-Tsung
ADMTEK Incorporated
Cady Albert De
Omar Omar A.
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